TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 168

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

2.17.6.1 Method of Developing the Control Program in the RAM Area
FLASH beforehand or should load from external device by using peripheral function
(Example: UART, SIO etc). Given below is an example of developing the control
program in the RAM area.
(1) Example of developing and writing the control program to the RAM area
To develop the program in RAM, the write control program should be stored in
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Set the EEPCR with “CBH” (to disable a write to the FLASH).
11. Jump to the FLASH area (Main program).
Note: See (2), “Method of specifying an address for a write to the FLASH,” for a
For the emulation chip, set the EEPEVA register with an optimum time value
according to the operating frequency.
Transfer the write control program to the RAM area.
Release an address trap in the RAM area (Set up the WDTCR1 and WDTCR2
registers).
Jump to the RAM area.
Monitor the EEPSR<EWUPEN>. If it is “0”, set the EEPCR<MNPWDW> to
“1”, and then start and keep polling until the EEPSR<EWUPEN> becomes
“1”.
Clear the interrupt master enable flag (IMF ← “0”).
Set the EEPCR with “3BH” (to enable a write to the FLASH).
Execute a write instruction for 64 bytes to the FLASH area.
Start and keep polling by software until the EEPSR<BFBUSY> becomes “0”.
(Upon completion of an erase and write to the FLASH cells, the
EEPSR<BFBUSY> is set to “1”. For the FLASH product, the required write
time is typically 4 ms. For the emulation chip, it is the value specified in the
EEPEVA register.)
description about the FLASH address to be specified at step 8 above.
86FM48-164
TMP86FM48
2007-08-24