TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 46

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

External interrupt control register
INT0
INT1
INT2
INT3
INT5
Source
Note 1: If a noiseless signal is input to the external interrupt pin in the NORMAL 1/2 or IDLE 1/2 mode, the
Note 2: Even if the falling edge of
Note 3: When data changed and did a change of I/O when used external interrupt ports as a normal ports,
Note 4: The maximum time from modifying INT1NC until a noise reject time is changed is 2
EINTCR
(0037
H
)
INT1
INT2
INT3
INT
INT
maximum time from the edge of input signal until the IL is set is as follows:
interrupt request signal occurs incorrectly. Handling of prohibition of interrupt enable register (EIR)
is necessary.
Note 1: fc: High-frequency clock [Hz], *: Don’t care
Note 2: When the system clock frequency is switched between high and low or when the external interrupt control
INT1NC INT0EN
0
5
Pin
INT1NC
INT0EN
INT3ES
INT2ES
INT1ES
7
(1) INT1 pin
(2) INT2, INT3 pin
register (EINTCR) is overwritten, the noise canceller may not operate normally. It is recommended that
external interrupts are disabled using the interrupt enable register (EIR).
Function Pin
P00
P01
P02
P14/TC3
P20/
Secondary
Noise reject time select
P00/
INT3 to INT1 edge select
6
STOP
INT
0
Figure 1.5.5 External Interrupt Control Register
5
pin configuration
Enable Conditions
IMF = 1, EF
INT0EN = 1
IMF•EF
IMF•EF
IMF•EF
IMF•EF
INT0
Table 1.5.2 External Interrupts
4
6
8
13
21
55/fc [s] (INT1NC = 1), 199/fc [s] (INT1NC = 0)
31/fc [s]
= 1
= 1
= 1
= 1
pin input is detected at INT0EN = 0, the interrupt latch IL
4
INT3ES INT2ES INT1ES
= 1,
3
86FM48-42
0: Pulses of less than 63/fc [s] are eliminated as noise
1: Pulses of less than 15/fc [s] are eliminated as noise
0: P00 input/output port
1:
0: Rising edge
1: Falling edge
INT
2
0
Falling edge
Falling edge
Falling edge
Rising edge
pin (Port P00 should be set to an input mode)
Edge
or
1
Pulses of less than 2/fc [s] are eliminated as
noise. Pulses of 7/fc [s] or more are
considered to be signals. In the SLOW or the
SLEEP mode, pulses of less than 1/fs [s] are
eliminated as noise. Pulses of 3.5/fs [s] or
more are considered to be signals.
Pulses of less than 15/fc or 63/fc [s] are
eliminated as noise. Pulses of 49/fc or 193/fc
[s] or more are considered to be signals.
In the SLOW or the SLEEP mode, pulses of
less than 1/fs [s] are eliminated as noise.
Pulses of 3.5/fs [s] or more are considered to
be signals.
Pulses of less than 7/fc [s] are eliminated as
noise. Pulses of 25/fc [s] or more are
considered to be signals.
In the SLOW or the SLEEP mode, pulses of
less than 1/fs [s] are eliminated as noise.
Pulses of 3.5/fs [s] or more are considered to
be signals.
Pulses of less than 2/fc [s] are eliminated as
noise. Pulses of 7/fc [s] or more are
considered to be signals. In the SLOW or the
SLEEP mode, pulses of less than 1/fs [s] are
eliminated as noise. Pulses of 3.5/fs [s] or
more are considered to be signals.
0
(Initial value: 00** 000*)
Digital Noise Reject
TMP86FM48
6
/fc.
2007-08-24
4
is not set.
R/W