TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 68

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

2.4.3
2.4.4
Clock
Binary counter
Overflow
INTWDT interrupt
(WDTCR1<WDTOUT> = “0”)
Internal reset
(WDTCR1<WDTOUT> = ”1”)
Table 2.4.1 Watchdog Timer Detection Time (Example: fc = 16 MHz, fs = 32.768 kHz)
Watchdog Timer Interrupt (INTWDT)
Watchdog Timer Reset
EIR. If a watchdog timer interrupt or a software interrupt is already accepted, however, the
new watchdog timer interrupt waits until the previous interrupt processing is completed
(The end of the [RETN] instruction execution).
interrupt source with WDTOUT.
is reseted. When the watchdog timer reset is generated, the flash reset is also generated.
Therefore, the maximum reset period is 24/fc [s] + 2
Note: The high-frequency clock oscillator also immediately turns on when a watchdog timer
This is a non-maskable interrupt which can be accepted regardless of the contents of the
The stack pointer (SP) should be initialized before using the watchdog timer output as an
If the watchdog timer reset request occur, a reset is generated and the internal hardware
reset is generated in SLOW mode. In this case, the reset time may include a certain
amount of error if there is any fluctuation of the oscillation frequency at starting the
high-frequency clock oscillation. Therefore, the reset time must be considered an
approximated value.
WDTT
Example: Disables watchdog timer
Example: Watchdog timer interrupt setting up
00
01
10
11
1
Figure 2.4.3 Watchdog Timer Interrupt/Reset
DV7CK = 0
Write 4E
2
524.288 m
131.072 m
DI
LD
LDW
32.768 m
LD
LD
2.097
NORMAL1/2 Mode
Watchdog Timer Detection Time [s]
H
3
to WDTCR2
2
17
/fc
(WDTCR2), 4EH
(WDTCR1), 0B101H
SP, 023FH
(WDTCR1), 00001000B
86FM48-64
0
DV7CK = 1
250 m
62.5 m
1
4
1
2
19
/fc [s]
10
2
/fc [s] (65.5 µs at 16.0 MHz).
SLOW Mode
;
;
;
;
;
250 m
IMF ← 0
Clear the binary counter
WDTEN ← 0, WDTCR2 ← Disable code
Sets the stack pointer
WDTOUT ← 0
62.5 m
4
1
3
Reset generate
0
(WDTT = 11
TMP86FM48
2007-08-24
B
)