TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 147

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

AD Converter Control Register 1
AD Converter Control Register 2
ADCCR1
(000E
ADCCR2
(000F
H
H
)
)
Note 1: Select analog input when AD converter stops (ADCDR2<ADBF> = “0”).
Note 2: When the analog input is all use disabling, the AINDS should be set to “1”.
Note 3: During conversion, do not perform output instruction to maintain a precision for all of the pins. And port near
Note 4: The ADRS is automatically cleared to “0” after starting conversion.
Note 5: Do not set ADRS newly again during AD conversion. Before setting ADRS newly again, check
Note 6: After STOP or SLOW mode are started, AD converter control register 1 (ADCCR1) is all initialized.
Note 1: Settings for “−” in the above table are inhibited.
Note 2: Set conversion time by analog reference voltage (V
Note 3: Always set bit0 in ADCCR2 to “0” and set bit4 in ADCCR2 to “1”.
Note 4: When a read instruction for ADCCR2, bit6 to 7 in ADCCR2 read in as undefined data.
Note 5: fc: High-frequency clock [Hz]
Note 6: After STOP or SLOW mode are started, AD converter control register 2 (ADCCR2) is all initialized.
ADRS
IREFON
AINDS
ADRS
SAIN
AMD
ACK
7
7
to analog input, do not input intense signaling of change.
ADCDR2<EOCF> to see that the conversion is completed or wait until the interrupt signal (INTADC) is
generated (e.g., interrupt handling routine).
Therefore, set the ADCCR1 newly again after exiting these modes.
Therefore, set the ADCCR2 newly again after exiting these modes.
AD conversion start
AD operating mode
Analog input control
Analog input channel select
connection control
AD conversion time select
6
6
DA converter (Ladder resistor)
AMD
IREFON
V
V
AREF
AREF
5
5
Figure 2.15.2 AD Converter Control Register
= 2.7 to 3.6 V (31.2 µ or more)
= 1.8 to 3.6 V (124.8 µ or more)
AINDS
“1”
4
4
3
3
86FM48-143
0000: Selects AIN00
0001: Selects AIN01
0010: Selects AIN02
0011: Selects AIN03
0100: Selects AIN04
0101: Selects AIN05
0110: Selects AIN06
0111: Selects AIN07
Inputting current to the ladder resistor
ACK
000
001
010
011
100
101
110
111
00: AD operation disable
01: Software start mode
10: Reserved
11: Repeat mode
ACK
0: −
1: Start
0: Analog input enable
1: Analog input disable
0: Connected only during AD conversion
1: Always connected
2
2
SAIN
Conversion
1248/fc
156/fc
312/fc
624/fc
39/fc
78/fc
time
AREF
1
1
) as follows.
16 MHz
39.0 µs 78.0 µs 156.0 µs
78.0 µs 156.0 µs
“0”
0
0
fc =
−
−
−
−
1000: Selects AIN10
1001: Selects AIN11
1010: Selects AIN12
1011: Selects AIN13
1100: Selects AIN14
1101: Selects AIN15
1110: Selects AIN16
1111: Selects AIN17
Reserved
Reserved
(Initial value: 0001 0000)
(Initial value: **00 0000)
39.0 µs 78.0 µs
8 MHz
fc =
−
−
−
39.0 µs 156.0 µs
4 MHz
fc =
−
−
−
39.0 µs
78.0 µs
1 MHz
fc =
TMP86FM48
−
−
−
2007-08-24
R/W
R/W