TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 19

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TMP86xy48UG/FG

Manufacturer Part Number
TMP86xy48UG/FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP86xy48UG/FG

Package
LQFP64/QFP64
Rom Types (m=mask,p=otp,f=flash)
F/E
Rom Size
32
Ram Size
2K
Driver Led
11
Driver Lcd
-
Spi/sio Channels
1
Uart/sio Channels
1
I2c/sio Channels
1
High-speed Serial Output
2
Adc 8-bit Channels
-
Adc 10-bit Channels
16
Da Converter Channels
-
Timer Counter 18-bit Channel
-
Timer Counter 16-bit Channel
2
Timer Counter 8-bit Channel
2
Motor Channels
-
Watchdog Timer
Y
Dual Clock
Y
Clock Gear
-
Number Of I/o Ports
54
Power Supply (v)
2.7 to 3.6
Single
Clock
Clock
Dual
(a) Single clock mode
(b) Dual clock mode
Operating Mode
RESET
NORMAL1
IDLE1
IDLE0
STOP
NORMAL2
IDLE2
SLOW2
SLEEP2
SLOW1
SLEEP1
SLEEP0
STOP
SLEEP2
SLEEP1
IDLE1
IDLE2
mode
mode
mode
mode
Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW;
Note 2: The mode is released by falling edge of TBTCR<TBTCK> setting.
IDLE0, IDLE1 and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP.
High Frequency Low Frequency
Oscillation
Oscillation
SYSCR2<IDLE> = “1”
SYSCR2<IDLE> = “1”
SYSCR2<IDLE> = “1”
SYSCR2<IDLE> = “1”
SYSCR2<TGHALT> = “1”
Stop
Stop
SYSCR2<SYSCK> = “0”
SYSCR2<XTEN> = “0”
SYSCR2<XTEN> = “1”
Interrupt
Interrupt
Interrupt
Figure 1.4.6 Operating Mode Transition Diagram
Interrupt
Oscillator
Oscillation
Stop
Stop
(Note 2)
NORMAL1
NORMAL2
86FM48-15
SLOW2
SLEEP0
SLOW1
Operate with high frequency
IDLE0
mode
mode
mode
mode
Operate with low frequency
Operate with low frequency
mode
mode
SYSCR2<XTEN> = “1”
SYSCR2<SYSCK> = “1”
(Note 2)
CPU Core
SYSCR2<XEN> = “0”
SYSCR2<TGHALT> = “1”
Operate
Reset
Halt
Halt
Halt
Halt
STOP
STOP
SYSCR1<STOP> = “1”
SYSCR1<STOP> = “1”
STOP
SYSCR1<STOP> = “1”
pin input
pin input
pin input
Reset release
Operate
Operate
Reset
TBT
Halt
Halt
Peripherals
Operate
Operate
RESET
Other
Reset
STOP
Halt
Halt
TMP86FM48
Cycle Time
2007-08-24
Machine
4/fc [s]
4/fc [s]
4/fs [s]

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