TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 118

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

INTSBI interrupt
INTSBI interrupt
SDA pin
SCL pin
SDA pin
SCL pin
request
(3) 1-word data transfer
PIN
PIN
completed, and determine whether the mode is a master or slave.
a.
Check the MST by the INTSBI interrupt process after an 1-word data transfer is
When the MST is “1” (Master mode)
1.
2.
Check the TRX and determine whether the mode is a transmitter or receiver.
Figure 2.12.12 Example of when BC = “000”, ACK = “1”
Figure 2.12.13 Example of when BC = “000”, ACK = “1”
Implement the process to generate a stop condition (Described later) and
terminate data transfer.
transmitted data is other than 8 bits, set the BC, set the ACK to “1”, and write
the transmitted data to the SBIDBR. After writing the data, the PIN becomes
“1”, a serial clock pulse is generated for transferring a next 1 word of data
from the SCL pin, and then the 1 word of data is transmitted. After the data is
transmitted, and an INTSBI interrupt request occurs. The PIN become “0”
and the SCL pin is set to low level. If the data to be transferred is more than
one word in length, repeat the procedure from the LRB test above.
Set the ACK to “1” and read the received data from the SBIDBR (Reading data
is undefined immediately after a slave address is sent). After the data is read,
the PIN becomes “1”. A serial bus interface circuit outputs a serial clock pulse
to the SCL to transfer next 1-word of data and sets the SDA pin to “0” at the
acknowledge signal timing.
bus interface circuit outputs a clock pulse for 1-word of data transfer and the
acknowledge signal each time that received data is read from the SBIDBR.
D7
D7
When the TRX is “1” (Transmitter mode)
When the TRX is “0” (Receiver mode)
Read SBIDBR
Write to SBIDBR
1
1
Test the LRB. When the LRB is “1”, a receiver does not request data.
When the LRB is “0”, the receiver requests next data. When the next
When the next transmitted data is other than of 8 bits, set the BC again.
An INTSBI interrupt request occurs and the PIN becomes “0”. Then a serial
D6
D6
2
2
D5
D5
3
3
86FM48-114
D4
D4
4
4
D3
D3
5
5
D2
D2
6
6
D1
D1
7
7
D0
D0
8
8
9
9
Acknowledge
signal to a
transmitter
Acknowledge
signal from a
receiver
New D7
TMP86FM48
2007-08-24