TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 28

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

•
•
(a) Normal release mode (IMF = “0”)
(b) Interrupt release mode (IMF = “1”)
Start the IDLE1/2 and SLEEP1/2 modes
Release the IDLE1/2 and SLEEP1/2 modes
release mode. These modes are selected by interrupt master enable flag (IMF).
automatically cleared to “0” and the operation mode is returned to the mode
preceding IDLE1/2 and SLEEP1/2 modes.
EEPCR<ATPWDW> = “0”, the CPU wait period for stabilizing of the power supply
of Flash control circuit is added before the operation mode is returned to the
preceding modes. The CPU wait time of IDLE1/2 is 2
mode is 2
mode.
the individual interrupt enable flag (EF). After the interrupt is generated, the
program operation is resumed from the instruction following the IDLE1/2 and
SLEEP1/2 modes start instruction. Normally, the interrupt latches (IL) of the
interrupt source used for releasing must be cleared to “0” by load instructions.
with the individual interrupt enable flag (EF). After the interrupt is processed,
the program operation is resumed from the instruction following the instruction,
which starts IDLE1/2 and SLEEP1/2 modes.
Note: When a watchdog timer interrupts is generated immediately before IDLE1/2
RESET
Note: During CPU wait, though CPU operations remain halted, but the peripheral
When IDLE1/2 and SLEEP1/2 modes start, set SYSCR2<IDLE> to “1”.
IDLE1/2 and SLEEP1/2 modes include a normal release mode and an interrupt
After releasing IDLE1/2 and SLEEP1/2 modes, the SYSCR2<IDLE> is
When
IDLE1/2 and SLEEP1/2 modes can also be released by inputting low level on the
IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled by
IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled
and SLEEP1/2 mode are started, the watchdog timer interrupt will be
processed but IDLE1/2 and SLEEP1/2 mode will not be started.
function operation is resumed. Therefore in this time, though the interrupt
latch might be set, interrupt operation is not executed until the CPU wait is
finished.
pin. After releasing reset, the operation mode is started from NORMAL1
3
/fs [s].
the
IDLE1/2
86FM48-24
and
SLEEP1/2
modes
10
/fc [s] and that of SLEEP1/2
are
started
TMP86FM48
2007-08-24
with
the