TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 75

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

(2) External trigger timer mode
the TC1 pin input. Either the rising or falling edge can be selected with TC1S. Source
clock is an internal clock. The contents of TC1DRA is compared with the contents of up
counter. If a match is found, an INTTC1 interrupt is generated, and the counter is
cleared to “0” and halted. The counter is restarted by the selected edge of the TC1 pin
input.
trigger edge to start counting clears the counter, and the counter is stopped. Inputting
a constant pulse width can generate interrupts. When TC1CR<METT1> is “0”, the
reverse directive edge input is ignored. The TC1 pin input edge before a match
detection is also ignored.
rejected as noise. A pulse width of 12/fc [s] or more is required for edge detection in
NORMAL1/2 or IDLE1/2 mode. The noise rejection circuit is turned off in SLOW1/2
and SLEEP1/2 modes. But, a pulse width of one machine cycle or more is required.
In this mode, counting up is started by an external trigger. This trigger is the edge of
When TC1CR<METT1> is “1”, inputting the edge to the reverse direction of the
The TC1 pin input has the noise rejection; therefore, pulses of 4/fc [s] or less are
Example 1: Detects rising edge in TC1 pin input and generates an interrupt 100 µs later.
Example 2: Generates an interrupt, inputting “L” level pulse (pulse width: 4 ms or more) to the TC1 pin.
(at fc = 16 MHz, DV7CK = 0)
(at fc = 16 MHz)
DI
LDW
SET
EI
LD
LD
DI
LDW
SET
EI
LD
LD
(TC1DRA), 00C8H
(EIRL). 5
(TC1CR), 00001000B
(TC1CR), 00101000B
(TC1DRA), 1F40H
(EIRL). 5
(TC1CR), 01001000B
(TC1CR), 01111000B
86FM48-71
;
;
;
;
;
;
;
;
;
;
;
;
IMF = “0”
100 µs ÷ 2
INTTC1 interrupt enable
IMF = “1”
TFF1 = “0”, TC1CK = “10”, TC1M = “00”
TC1 external trigger start, METT1 =“0”
IMF = “0”
4 ms ÷ 2
INTTC1 interrupt enable
IMF = “1”
TFF1 = “0”, TC1CK = “10”, TC1M = “00”
TC1 external trigger start, METT1 = 1
3
/fc = 1F40H
3
/fc = C8H
TMP86FM48
2007-08-24