TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 83

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

(0025, 0024H)
TC2DR
(0013H)
TC2CR
R/W
2.8.2
Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
Note 2: When writing to the Timer Register 2 (TC2DR), always write to the lower side (TC2DRL) and then the upper
Note 3: The timer register 2 (TC2DR) uses the value previously set in it for coincidence detection until data is written
Note 4: Set the mode and source clock when the TC2 stops (TC2S = 0).
Note 5: Values to be loaded to the timer register must satisfy the following condition.
Note 6: If a read instruction is executed for TC2CR, read data of bit 7, 6 and 1 are unstable.
Note 7: The high-frequency clock(fc) can be selected only when the timer mode at SLOW2 mode is selected.
Note 8: On entering STOP mode, the TC2 start control (TC2S) is cleared to “0” automatically. So, the timer stops.
Control
16-bit timer register 2 (TC2DR). Reset does not affect TC2DR.
15
TC2CK
7
TC2M
TC2S
The timer/counter 2 is controlled by a timer/counter 2 control register (TC2CR) and a
14
side (TC2DRH) in that order. Writing to only the lower side (TC2DRL) or the upper side (TC2DRH) has no
effect.
to the upper side (TC2DRH) after writing data to the lower side (TC2DRL).
Once the STOP mode has been released, to start using the timer counter, set TC2S again.
6
TC2 operating mode select
TC2 source clock select [Hz]
TC2 start control
TC2S
Figure 2.8.2 Timer Register 2 and TC2 Control Register
13
5
TC2DR > 1 (TC2DR
TC2DRH (0025H)
12
4
TC2CK
11
3
10
2
15 to
86FM48-79
0:
1:
000
001
010
011
100
101
110
111
0:
1:
TC2DR
1
9
Timer/event counter mode
Window mode
Stop and counter clear
Start
TC2M (Initial value: **00 00*0)
NORMAL1/2, IDLE1/2 mode
11
DV7CK = 0
0
8
> 1 at warm up)
fc/2
fc/2
fc/2
fc/2
fs
−
23
13
8
3
7
External clock (TC2 pin input)
6
DV7CK = 1
fs/2
fs/2
fc/2
fc/2
fs
−
Reserved
15
5
8
3
5
TC2DRL (0024H)
4
fc (Note 7)
SLOW1/2
mode
fs/2
fs/2
−
−
−
15
5
3
SLEEP1/2
2
mode
fs/2
fs/2
−
−
−
−
TMP86FM48
15
5
2007-08-24
1
R/W
0