TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 41

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

Interrupt request
Interrupt latch (IL)
IMF
Execute Instruction
PC
SP
1.5.1
Note 1: a: return address entry address, b: entry address, c: address which RETI instructrion is stored
Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at
Interrupt Sequence
interrupt latch is cleared to “0” by resetting or an instruction. Interrupt acceptance
sequence requires 8-machine cycles (4 µs at 8.0 MHz) after the completion of the current
instruction. The interrupt service task terminates upon execution of an interrupt return
instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts).
Figure 1.5.3 shows the timing chart of interrupt acceptance processing.
(1) Interrupt acceptance processing is packaged as follows.
Figure 1.5.3 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction
An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or
1-machine cycle
Note: When the contents of PSW are saved on the stack, the contents of IMF are also
1.
2.
3.
4.
5.
a − 1
the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt
latch is set.
Instruction
The interrupt master enable flag (IMF) is cleared to “0” in order to disable the
acceptance of any following interrupt.
The interrupt latch (IL) for the interrupt source accepted is cleared to “0”.
The contents of the program counter (PC) and the program status word, including
the interrupt master enable flag (IMF), are saved (Pushed) on the stack in
sequence of PSW + IMF, PCH, PCL. Meanwhile, the stack pointer (SP) is
decremented by 3.
The entry address (Interrupt vector) of the corresponding interrupt service
program, loaded on the vector table, is transferred to the program counter.
The instruction stored at the entry address of the interrupt service program is
executed.
Execute
a
saved.
a + 1
n
Interrupt acceptance
a
n − 1 n − 2
86FM48-37
b
b + 1 b + 2 b + 3
Instruction
Execute
n − 3
Interrupt service task
c + 1
Execute RETI instruction
n − 2 n − 1
c + 2
a
a + 1 a + 2
n
TMP86FM48
2007-08-24