TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 135

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

SIO1CR<SIOS>
SIO1SR<SIOF>
SIO1SR<SEF>
input
SI1 pin
SIO1SR<RXF>
SIO1SR<RXERR>
INTSIO1
interrupt
request
SIO1RDB
SCK1
pin
A7
4. Receive error processing
A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1
Start shift
operation
Figure 2.13.15 Example of Receive Error Processing
Receive errors occur on the following situation. To protect SIO1RDB and the
shift
SIO1SR<RXERR> is “1”.
•
Shift operation is finished before reading out received data from
SIO1RDB at SIO1SR<RXF> is “1” in an external clock operation.
If receive error occurs, set the SIOCR1<SIOS> to “0” for reading the data
that received immediately before error occurence. And read the data
from SIO1RDB. Data in shift register (at errors occur) can be read by
reading the SIO1RDB again.
When SIO1SR<RXERR> is cleared to “0” after reading the received data,
SIO1SR<RXF> is cleared to “0”.
After clearing SIO1CR<SIOS> to “0”, when 8-bit serial clock is input to
confirm that SIO1SR<SIOF> is cleared to “0”.
If the receive error occurs, set the SIOCR1<SIOINH> to “1” for stopping
the receive operation immediately. In this case, SIO1CR<SIOS>,
SIO1SR register, SIO1RDB register and SIO1TDB register are
initialized.
Note: If receive error is not corrected, an interrupt request does not
SCK1
register
pin, receive operation is stopped. To restart the receive operation,
generate after the error occurs.
A
contents,
Start shift
operation
86FM48-131
the
Reading received
data A
B0
received
C7
Start shift
operation
C6 C5 C4 C3 C2 C1 C0
B
Reading received
data B
data
is
Write a “0” after reading the
received data when a receive
error occurs.
ignored
TMP86FM48
2007-08-24
while
the