TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 14

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

SYSCR2<SYSCK>
Timer/counters 1
Timer/counters 2
Timer/counters 3
Timer/counters 5
TBTCR<DV7CK>
Serial interface
High-frequency
Low-frequency
1.4.2
clock fs
clock fc
Timing Generator
peripheral hardware from the basic clock (fc or fs). The timing generator provides the
following functions.
a.
b.
c.
d.
e.
f.
(1) Configuration of timing generator
The timing generator generates the various system clocks supplied to the CPU core and
Generation of main system clock
Generation of divider output (
Generation of source clocks for time base timer
Generation of source clocks for watchdog timer
Generation of internal source clocks for timer/counters and serial interface
Generation of warm-up clocks for releasing STOP mode
system clock generator, and machine cycle counters.
TBTCR<DV7CK>, that is shown in Figure 1.4.4. As reset and STOP mode
started/canceled, the prescaler and the divider are cleared to “0”.
The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main
An input clock to the 7th stage of the divider depends on the operating mode,
1
fc/4
2
Main system clock generator
Figure 1.4.3 Configuration of Timing Generator
1 2 3 4 5 6
86FM48-10
plexer
Multi-
A
B
S
Y
DVO
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
) pulses
fc or fs
Divider
Machine cycle counters
B0
B1
A0 Y0
A1 Y1
S
Multiplexer
TMP86FM48
Watchdog timer
Time base timer
Divider output
circuit
Warm-up
controller
2007-08-24