TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 62
TMP86xy48UG/FG
Manufacturer Part Number
TMP86xy48UG/FG
Description
Manufacturer
Toshiba
Datasheet
1.TMP86XY48UGFG.pdf
(207 pages)
Specifications of TMP86xy48UG/FG
Package
LQFP64/QFP64
Rom Types (m=mask,p=otp,f=flash)
F/E
Rom Size
32
Ram Size
2K
Driver Led
11
Driver Lcd
-
Spi/sio Channels
1
Uart/sio Channels
1
I2c/sio Channels
1
High-speed Serial Output
2
Adc 8-bit Channels
-
Adc 10-bit Channels
16
Da Converter Channels
-
Timer Counter 18-bit Channel
-
Timer Counter 16-bit Channel
2
Timer Counter 8-bit Channel
2
Motor Channels
-
Watchdog Timer
Y
Dual Clock
Y
Clock Gear
-
Number Of I/o Ports
54
Power Supply (v)
2.7 to 3.6
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(1FE7
(0008
P8DR
P8CR
2.2.8
R/W
H
H
)
)
Data output (P8DR)
Data input (P8DR)
*: Don’t care.
Port P8 (P87 to P80)
one-bit unit. Input/output mode is specified by the P8 control register (P8CR).
P87
P8CR
7
P8CRi input
Port P8 is an 8-bit input/output port which can be configured as an input or an output in
When used as an output port, respective P8CR should be set to “1”.
When used as an input port, respective P8CR should be cleared to “0”.
During reset, the P8CR and P8DR are initialized to “0”. Table 2.2.4 shows a P8 state.
P8CR
OUTEN
0
1
1
P8CRi
STOP
P86
Port P8 I/O control
(Set for each bit individually)
6
P85
5
P8DR
D
*
0
1
Q
D
P84
4
Table 2.2.4 P8 Port State
Q
“0” (Output latch)
“1” (Output latch)
Figure 2.2.11 Port 8
Terminal input
P8DR read
P83
3
86FM48-58
0: Input mode or Analog input
1: Output mode
P82
2
P81
Output
1
High-Z
High
Low
P80
0
Note: i = 7 to 0
P8i
(Initial value: 0000 0000)
(Initial value: 0000 0000)
Output mode
Output mode
Input mode
Remark
TMP86FM48
2007-08-24
R/W
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