SAM3N0C Atmel Corporation, SAM3N0C Datasheet - Page 66

no-image

SAM3N0C

Manufacturer Part Number
SAM3N0C
Description
Manufacturer
Atmel Corporation
Datasheets
10.6.3
10.6.3.1
10.6.3.2
10.6.3.3
10.6.4
66
SAM3N
Exception handlers
Vector table
Interrupt Service Routines (ISRs)
Fault handlers
System handlers
For more information about hard faults, memory management faults, bus faults, and usage
faults, see
The processor handles exceptions using:
Interrupts IRQ0 to IRQ32 are the exceptions handled by ISRs.
Hard fault, memory management fault, usage fault, bus fault are fault exceptions handled by the
fault handlers.
NMI, PendSV, SVCall SysTick, and the fault exceptions are all system exceptions that are han-
dled by system handlers.
The vector table contains the reset value of the stack pointer, and the start addresses, also
called exception vectors, for all exception handlers.
the exception vectors in the vector table. The least-significant bit of each vector must be 1, indi-
cating that the exception handler is Thumb code.
“Interrupt Clear-enable Registers” on page
“Fault handling” on page
70.
154.
Figure 10-3 on page 67
11011A–ATARM–04-Oct-10
shows the order of

Related parts for SAM3N0C