SAM3N0C Atmel Corporation, SAM3N0C Datasheet - Page 474

• Manufacturer Part Number: SAM3N0C
• Manufacturer: Atmel Corporation

28.8.10
Figure 28-15. TWI Write Operation with Single Data Byte without Internal Address
474
474
SAM3N
SAM3N
Read-write Flowcharts
The following flowcharts shown in
28-18 on page
read and write operations. A polling or interrupt method can be used to check the status bits.
The interrupt method requires that the interrupt enable register (TWI_IER) be configured first.
477,
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
- Device slave address (DADR)
Set the Master Mode register:
TWI_CR = MSEN + SVDIS
Figure 28-19 on page 478
Write ==> bit MREAD = 0
TWI_THR = Data to send
Set the Control register:
Write STOP Command
Load Transmit register
- Transfer direction bit
Read Status register
Read Status register
(Needed only once)
TWI_CR = STOP
Transfer finished
- Master enable
TXCOMP = 1?
Set TWI clock
TXRDY = 1?
Yes
Yes
BEGIN
Figure 28-16 on page
and
No
No
Figure 28-20 on page 479
475,
Figure 28-17 on page
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
give examples for
476,
Figure