SAM3N0C Atmel Corporation, SAM3N0C Datasheet - Page 464

• Manufacturer Part Number: SAM3N0C
• Manufacturer: Atmel Corporation

28.2
28.3
464
464
Embedded Characteristics
List of Abbreviations
SAM3N
SAM3N
Note:
Table 28-2.
Abbreviation
TWI
A
NA
P
S
Sr
SADR
ADR
R
W
• Two TWIs
• Compatible with Atmel Two-wire Interface Serial Memory and I²C Compatible Devices
• One, Two or Three Bytes for Slave Address
• Sequential Read-write Operations
• Master, Multi-master and Slave Mode Operation
• Bit Rate: Up to 400 Kbits
• General Call Supported in Slave mode
• SMBUS Quick Command Supported in Master Mode
• Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data
• Connection to DMA Controller (DMAC) Channel Capabilities Optimizes Data Transfers in
Transfers in Master Mode Only
Master Mode Only
– One Channel for the Receiver, One Channel for the Transmitter
– Next Buffer Support
See
Table 28-1
Abbreviations
for details on compatibility with I²C Standard.
Description
Two-wire Interface
Acknowledge
Non Acknowledge
Stop
Start
Repeated Start
Slave Address
Any address except SADR
Read
Write
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
(Note:)