SAM3N0C Atmel Corporation, SAM3N0C Datasheet - Page 394

• Manufacturer Part Number: SAM3N0C
• Manufacturer: Atmel Corporation

Figure 26-7. Event Detector on Input Lines (Figure represents line 0)
26.5.10.1
394
394
Resynchronized input on line 0
SAM3N
SAM3N
Example
When an input Edge or Level is detected on an I/O line, the corresponding bit in PIO_ISR (Inter-
rupt Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller
interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired
together to generate a single interrupt signal to the . Nested Vector Interrupt Controller (NVIC).
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that
all the interrupts that are pending when PIO_ISR is read must be handled. When an Interrupt is
enabled on a “Level”, the interrupt is generated as long as the interrupt source is not cleared,
even if some read accesses in PIO_ISR are performed.
If generating an interrupt is required on the following:
The configuration required is described below.
• Rising edge on PIO line 0
• Falling edge on PIO line 1
• Rising edge on PIO line 2
• Low Level on PIO line 3
• High Level on PIO line 4
• High Level on PIO line 5
• Falling edge on PIO line 6
• Rising edge on PIO line 7
• Any edge on the other lines
Level is selected in the PIO_ELSR). The current status of this selection is accessible through
the PIO_FRLHSR (Fall/Rise - Low/High Status Register).
PIO_REHLSR[0]
PIO_FELLSR[0]
Rising Edge
Falling Edge
High Level
Detector
Low Level
Detector
Detector
Detector
Detector
Edge
PIO_FRLHSR[0]
0
0
1
1
PIO_LSR[0]
PIO_ESR[0]
PIO_ELSR[0]
1
0
PIO_AIMER[0]
PIO_AIMDR[0]
PIO_AIMMR[0]
1
0
Event detection on line 0
Event Detector
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10