SAM3N0C Atmel Corporation, SAM3N0C Datasheet - Page 173

• Manufacturer Part Number: SAM3N0C
• Manufacturer: Atmel Corporation

10.21.7
• SEVONPEND
Send Event on Pending bit:
0 = only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
1 = enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not
waiting for an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an
• SLEEPDEEP
Controls whether the processor uses sleep or deep sleep as its low power mode:
0 = sleep
1 = deep sleep.
• SLEEPONEXIT
Indicates sleep-on-exit when returning from Handler mode to Thread mode:
0 = do not sleep when returning to Thread mode.
1 = enter sleep, or deep sleep, on return from an ISR.
Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
11011A–ATARM–04-Oct-10
31
23
15
7
System Control Register
Reserved
30
22
14
6
The SCR controls features of entry to and exit from low power state. See the register summary
in
Table 10-30 on page 164
29
21
13
5
SEVONPEND
SEV
28
20
12
instruction or an external event.
4
for its attributes. The bit assignments are:
Reserved
Reserved
Reserved
Reserved
27
19
11
3
SLEEPDEEP
26
18
10
2
SLEEONEXIT
25
17
9
1
SAM3N
Reserved
24
16
8
0
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