SAM3N0C Atmel Corporation, SAM3N0C Datasheet - Page 307

• Manufacturer Part Number: SAM3N0C
• Manufacturer: Atmel Corporation

21. Bus Matrix (MATRIX)
21.1
21.2
21.2.1
21.2.2
11011A–ATARM–04-Oct-10
Description
Embedded Characteristics
Matrix Masters
Matrix Slaves
The Bus Matrix implements a multi-layer AHB that enables parallel access paths between multi-
ple AHB masters and slaves in a system, which increases the overall bandwidth. Bus Matrix
interconnects 3 AHB Masters to 4 AHB Slaves. The normal latency to connect a master to a
slave is one cycle except for the default master of the accessed slave which is connected
directly (zero cycle latency).
The Bus Matrix user interface also provides a Chip Configuration User Interface with Registers
that allow to support application specific features.
The Bus Matrix of the SAM3N product manages 3 masters, which means that each master can
perform an access concurrently with others, to an available slave.
Each master has its own decoder, which is defined specifically for each master. In order to sim-
plify the addressing, all the masters have the same decodings.
Table 21-1.
The Bus Matrix of the SAM3N product manages 4 slaves. Each slave has its own arbiter, allow-
ing a different arbitration per slave.
List of Bus Matrix Slaves
Master 0
Master 1
Master 2
Slave 0
Slave 1
Slave 2
Slave 3
List of Bus Matrix Masters
Cortex-M3 Instruction/Data
Cortex-M3 System
Peripheral DMA Controller (PDC)
Internal SRAM
Internal ROM
Internal Flash
Peripheral Bridge
SAM3N
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