SAM3N0C Atmel Corporation, SAM3N0C Datasheet
SAM3N0C
Related parts for SAM3N0C
SAM3N0C Summary of contents
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Features • Core ® ® – ARM Cortex -M3 revision 2.0 running MHz ® – Thumb -2 instruction – 24-bit SysTick Counter – Nested Vector Interrupt Controller • Pin-to-pin compatible with AT91SAM7S legacy products (48- and ...
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SAM3N Description Atmel's SAM3N series is a member of a family of Flash microcontrollers based on the high per- formance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 48 MHz and features up to 256 ...
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SAM3N Block Diagram Figure 2-1. SAM3N 100-pin version Block Diagram System Controller TST PCK0-PCK2 XIN XOUT WDT RC OSC 12/8/4 MHz OSC 32k XOUT32 ERASE VDDIO NRST PIOA VDDCORE URXD0 UTXD0 URXD1 UTXD1 RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 ...
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Figure 2-2. SAM3N 64-pin version Block Diagram System Controller TST PCK0-PCK2 XIN 3-20 MHz XOUT WDT RC OSC 12/8/4 MHz SUPC OSC 32k XOUT32 RC 32k ERASE VDDIO RSTC NRST PIOA VDDCORE URXD0 UTXD0 URXD1 UTXD1 RXD0 TXD0 SCK0 RTS0 ...
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Figure 2-3. SAM3N 48-pin version Block Diagramz System Controller TST PCK0-PCK2 XIN XOUT WDT RC OSC 12/8/4 MHz OSC 32k XOUT32 ERASE VDDIO NRST PIOA VDDCORE URXD0 UTXD0 URXD1 UTXD1 RXD0 TXD0 SCK0 RTS0 CTS0 PWM[0:3] ADTRG AD[0..7] ADVREF 11011AS–ATARM–04-Oct-10 ...
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Signal Description Table 3-1 Table 3-1. Signal Description List Signal Name Function VDDIO Peripherals I/O Lines Power Supply Voltage Regulator, ADC and DAC Power VDDIN Supply VDDOUT Voltage Regulator Output VDDPLL Oscillator and PLL Power Supply Power the core, ...
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Table 3-1. Signal Description List (Continued) Signal Name Function Flash and NVM Configuration Bits Erase ERASE Command NRST Microcontroller Reset TST Test Mode Select URXDx UART Receive Data UTXDx UART Transmit Data PA0 - PA31 Parallel IO Controller A PB0 ...
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Table 3-1. Signal Description List (Continued) Signal Name Function MISO Master In Slave Out MOSI Master Out Slave In SPCK SPI Serial Clock SPI_NPCS0 SPI Peripheral Chip Select 0 SPI_NPCS1 - SPI Peripheral Chip Select SPI_NPCS3 TWDx TWIx Two-wire Serial ...
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Package and Pinout SAM3N4/2/1 series is pin-to-pin compatible with SAM3S products. Furthermore SAM3N4/2/1 devices have new functionalities referenced in italic 4.1 SAM3N4/2/1C Package and Pinout 4.1.1 100-lead LQFP Package Outline Figure 4-1. 4.1.2 100-ball LFBGA Package Outline The 100-Ball ...
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LQFP Pinout Table 4-1. 100-lead LQFP SAM3N4/2/1C Pinout 1 ADVREF 26 2 GND 27 3 PB0/AD4 28 4 PC29/AD13 29 5 PB1/AD5 30 6 PC30/AD14 31 7 PB2/AD6 32 8 PC31/AD15 33 9 PB3/AD7 34 10 VDDIN 35 ...
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LFBGA Pinout Table 4-2. 100-ball LFBGA SAM3N4/2/1C Pinout A1 PB1/AD5 A2 PC29 A3 VDDIO A4 PB9/PGMCK/XIN A5 PB8/XOUT C10 A6 PB13/DAC0 A7 DDP/PB11 A8 DDM/PB10 A9 TMS/SWDIO/PB6 A10 JTAGSEL B1 PC30 B2 ADVREF B3 GNDANA B4 PB14/DAC1 B5 ...
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SAM3N4/2/1B Package and Pinout Figure 4-3. Figure 4-4. SAM3N Summary 12 Orientation of the 64-pad QFN Package TOP VIEW Orientation of the 64-lead LQFP Package ...
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LQFP and QFN Pinout 64-pin version SAM3N devices are pin-to-pin compatible with SAM3S products. Furthermore, SAM3N products have new functionalities shown in italic in Table 4-3. 64-pin SAM3N4/2/1B Pinout 1 ADVREF 2 GND 3 PB0/AD4 4 PB1AD5 5 ...
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SAM3N4/2/1A Package and Pinout Figure 4-5. Figure 4-6. SAM3N Summary 14 Orientation of the 48-pad QFN Package TOP VIEW Orientation of the 48-lead LQFP Package ...
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LQFP and QFN Pinout Table 4-4. 48-pin SAM3N4/2/1A Pinout 1 ADVREF 13 2 GND 14 3 PB0/AD4 15 4 PB1/AD5 16 5 PB2/AD6 17 6 PB3/AD7 18 7 VDDIN 19 8 VDDOUT 20 9 PA17/PGMD5/AD0 21 10 PA18/PGMD6/AD1 ...
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Power Considerations 5.1 Power Supplies The SAM3N product has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals. Voltage ranges from 1.62V and 1.95V. • VDDIO pins: ...
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Figure 5-1. Figure 5-2. Note: Figure 5-3 Since the PIO state is preserved when in backup mode, any free PIO line can be used to switch off the external regulator by driving the PIO line at low level (PIO is ...
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Figure 5-3. 5.4 Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLL. The power management controller can be used to adapt the frequency ...
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Supply Monitor alarm • RTC alarm • RTT alarm 5.5.2 Wait Mode The purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a powered state for a startup time of ...
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Low Power Mode Summary Table The modes detailed above are the main low power modes. Each part can be set off sep- arately and wake up sources can be individually configured. of the configurations of the ...
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Wake-up Sources The wake-up events allow the device to exit backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power sup- ply and the SRAM power supply, if they ...
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Fast Start-Up The SAM3N allows the processor to restart in a few microseconds while the processor is in wait mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up inputs ...
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Input/Output Lines The SAM3N has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be ...
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Table 6-1. System I/O Configuration Pin List. SYSTEM_IO Default function bit number after reset 12 ERASE 7 TCK/SWCLK 6 TMS/SWDIO 5 TDO/TRACESWO 4 TDI - PA7 - PA8 - PB9 - PB8 Notes PB12 is used as PIO ...
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Test Pin The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM3N series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it ...
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Processor and Architecture 7.1 ARM Cortex-M3 Processor • Version 2.0 • Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit. • Harvard processor architecture enabling simultaneous instruction fetch with data load/store. • Three-stage pipeline. • Single ...
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Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths are forbidden or ...
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Debug and Test Features • Debug access to all memory and registers in the system, including Cortex-M3 register bank when the core is running, halted, or held in reset. • Serial Wire Debug Port (SW-DP) and Serial Wire JTAG ...
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Memories 8.1 Product Mapping Figure 8-1. SAM3N4/2/1 Product Mapping Code 0x00000000 Boot Memory 0x00400000 Internal Flash 1 MByte 0x00800000 bit band Internal ROM region 0x00C00000 Reserved 0x1FFFFFFF 11011AS–ATARM–04-Oct-10 Address Memory Space 0x40000000 0x00000000 0x40004000 Code 0x40008000 0x20000000 0x20100000 0x4000C000 ...
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Embedded Memories 8.2.1 Internal SRAM The SAM3N4 product embeds a total of 24-Kbytes high-speed SRAM. The SAM3N2 product embeds a total of 16-Kbytes high-speed SRAM. The SAM3N1 product embeds a total of 8-Kbytes high-speed SRAM. The SRAM is accessible ...
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Flash Speed The user needs to set the number of wait states depending on the frequency used. For more details, refer to the AC Characteristics sub section in the product Electrical Character- istics Section. 8.2.3.5 Lock Regions Several lock ...
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Fast Flash Programming Interface The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang program- ming with market-standard industrial programmers. The FFPI supports read, ...
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System Controller The System Controller is a set of peripherals, which allow handling of key elements of the sys- tem, such as power, resets, clocks, time, interrupts, watchdog, etc... See the System Controller block diagram in 11011AS–ATARM–04-Oct-10 SAM3N Summary ...
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Figure 9-1. System Controller Block Diagram VDDIO Zero-Power Power-on Reset Supply Monitor (Backup) WKUP0 - WKUP15 General Purpose Backup Registers SLCK SLCK XIN32 Xtal 32 kHz Oscillator XOUT32 Embedded 32 kHz RC Oscillator Backup Power Supply core_nreset NRST FSTT0 - ...
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System Controller and Peripherals Mapping Please refer to All the peripherals are in the bit band region and are mapped in the bit band alias region. 9.2 Power-on-Reset, Brownout and Supply Monitor The SAM3N embeds three features to monitor, ...
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The reset circuitry is based on a zero-power power-on reset cell and a brownout detector cell. The zero-power power-on reset allows the Supply Controller to start properly, while the soft- ware-programmable brownout detector allows detection of either a battery discharge ...
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Power Management Controller The Power Management Controller provides all the clock signals to the system. It provides: • the Processor Clock HCLK • the Free running processor clock FCLK • the Cortex SysTick external clock • the Master Clock ...
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SysTick Timer • 24-bit down counter • Self-reload capability • Flexible System timer 9.9 Real-time Timer • Real-time Timer, allowing backup of time with different accuracies – 32-bit Free-running back-up Counter – Integrates a 16-bit programmable prescaler running on ...
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Chip Identification • Chip Identifier (CHIPID) registers permit recognition of the device and its revision. Table 9-1. • JTAG ID: 0x05B2E03F 9.14 UART • Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – Independent ...
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Multi-drive option enables driving in open drain – Programmable pull up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Selection of the drive level • Synchronous ...
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Table 10-1. Peripheral Identifiers (Continued) Instance ID Instance Name 25 TC2 26 TC3 27 TC4 28 TC5 29 ADC 30 DACC 31 PWM 10.2 Peripheral Signals Multiplexing on I/O Lines The SAM3N product features 2 PIO controllers (48-pin and 64-pin ...
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PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A (PIOA) I/O Line Peripheral A Peripheral B PA0 PWM0 TIOA0 PA1 PWM1 TIOB0 PA2 PWM2 PA3 TWD0 NPCS3 PA4 TWCK0 TCLK0 PA5 RXD0 NPCS3 PA6 TXD0 PA7 RTS0 ...
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PIO Controller B Multiplexing Table 10-3. Multiplexing on PIO Controller B (PIOB) I/O Line Peripheral A Peripheral B PB0 PWM0 PB1 PWM1 PB2 URXD1 PB3 UTXD1 PB4 TWD1 PB5 TWCK1 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 ...
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PIO Controller C Multiplexing I/O Line Peripheral A Peripheral B PC0 PC1 PC2 PC3 PC4 NPCS1 PC5 PC6 PC7 NPCS2 PC8 PWM0 PC9 PWM1 PC10 PWM2 PC11 PWM3 PC12 PC13 PC14 PCK2 PC15 PC16 PCK0 PC17 PCK1 PC18 PWM0 ...
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Embedded Peripherals Overview 11.1 Serial Peripheral Interface (SPI) • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with – Serial memories, such as DataFlash and 3-wire EEPROMs – ...
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Support for two PDC channels with connection to receiver and transmitter (for 11.4 USART • Programmable Baud Rate Generator • 9-bit full-duplex synchronous or asynchronous serial communications – stop bits in Asynchronous Mode ...
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Two multi-purpose input/output signals • Two global registers that act on all three TC Channels • Quadrature decoder – Advanced line filtering – Position/revolution/speed • 2-bit Gray Up/Down Counter for Stepper Motor 11.6 Pulse Width Modulation Controller (PWM) • ...
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Package Drawings The SAM3N series devices are available in LQFP, QFN and LFBGA packages. Figure 12-1. 100-lead LQFP Package Drawing Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information. SAM3N ...
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Figure 12-2. 100-ball LFBGA Package Drawing 11011AS–ATARM–04-Oct-10 SAM3N Summary 49 ...
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Figure 12-3. 64- and 48-lead LQFP Package Drawing SAM3N Summary 50 11011AS–ATARM–04-Oct-10 ...
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Table 12-1. Symbol θ θ θ aaa bbb ccc ddd 11011AS–ATARM–04-Oct-10 48-lead LQFP Package Dimensions (in mm) Millimeter Min Nom – – ...
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Table 12-2. Symbol θ 1 θ 2 θ aaa bbb ccc ddd SAM3N Summary 52 64-lead LQFP Package Dimensions (in mm) ...
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Figure 12-4. 48-pad QFN Package Drawing 11011AS–ATARM–04-Oct-10 SAM3N Summary 53 ...
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Table 12-3. Symbol aaa bbb ccc SAM3N Summary 54 48-pad QFN Package Dimensions (in mm) Millimeter Min Nom Max – – 090 – – 0.050 – 0.65 0.70 ...
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Figure 12-5. 64-pad QFN Package Drawing 11011AS–ATARM–04-Oct-10 SAM3N Summary 55 ...
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Ordering Information Table 13-1. SAM3N4/2/1 Ordering Code MRL ATSAM3N4CA-AU A ATSAM3N4CA-CU A ATSAM3N4BA-AU A ATSAM3N4BA-MU A ATSAM3N4AA-AU A ATSAM3N4AA-MU A ATSAM3N2CA-AU A ATSAM3N2CA-CU A ATSAM3N2BA-AU A ATSAM3N2BA-MU A ATSAM3N2AA-AU A ATSAM3N2AA-MU A ATSAM3N1CA-AU A ATSAM3N1CA-CU A ATSAM3N1BA-AU A ATSAM3N1BA-MU ...
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Revision History Doc. Rev Comments 11011AS First issue 11011AS–ATARM–04-Oct-10 SAM3N Summary Change Request Ref. 57 ...
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