SAM3N0C Atmel Corporation, SAM3N0C Datasheet - Page 61

• Manufacturer Part Number: SAM3N0C
• Manufacturer: Atmel Corporation

10.5.5.2
10.5.6
10.5.6.1
10.5.7
10.5.7.1
10.5.7.2
11011A–ATARM–04-Oct-10
Memory endianness
Synchronization primitives
Directly accessing a bit-band region
Little-endian format
A Load-Exclusive instruction
A Store-Exclusive instruction
Reading a word in the alias region:
“Behavior of memory accesses” on page 57
word accesses to the bit-band regions.
The processor views memory as a linear collection of bytes numbered in ascending order from
zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored
word. or
In little-endian format, the processor stores the least significant byte of a word at the lowest-
numbered byte, and the most significant byte at the highest-numbered byte. For example:
The Cortex-M3 instruction set includes pairs of synchronization primitives. These provide a non-
blocking mechanism that a thread or process can use to obtain exclusive access to a memory
location. Software can use them to perform a guaranteed read-modify-write memory update
sequence, or for a semaphore mechanism.
A pair of synchronization primitives comprises:
Used to read the value of a memory location, requesting exclusive access to that location.
Used to attempt to write to the same memory location, returning a status bit to a register. If this
bit is:
0: it indicates that the thread or process gained exclusive access to the memory, and the write
succeeds,
1: it indicates that the thread or process did not gain exclusive access to the memory, and no
write is performed,
The pairs of Load-Exclusive and Store-Exclusive instructions are:
Address A
• 0x00000000 indicates that the targeted bit in the bit-band region is set to zero
• 0x00000001 indicates that the targeted bit in the bit-band region is set to 1
• the word instructions LDREX and STREX
A+1
A+2
A+3
“Little-endian format”
7
Memory
B0
B1
B2
B3
0
lsbyte
msbyte
31
B3
describes how words of data are stored in memory.
24 23
B2
Register
16 15
B1
describes the behavior of direct byte, halfword, or
8 7
B0
0
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