SAM3N0C Atmel Corporation, SAM3N0C Datasheet - Page 152

• Manufacturer Part Number: SAM3N0C
• Manufacturer: Atmel Corporation

152
SAM3N
The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Regis-
ters. For more information see the description of the NVIC_SetPriority function in
programming hints” on page
onto the interrupt registers and corresponding CMSIS variables that have one bit per interrupt.
Table 10-28. Mapping of interrupts to the interrupt variables
1.
Interrupts
0-32
• the 4-bit fields of the Interrupt Priority Registers map to an array of 4-bit integers, so that the
array IP[0] to IP[32] corresponds to the registers IPR0-IPR8, and the array entry IP[n] holds
the interrupt priority for interrupt n.
Each array element corresponds to a single NVIC register, for example the element
ICER[0] corresponds to the ICER0 register.
CMSIS array elements
Set-enable
ISER[0]
Clear-enable
ICER[0]
163.
Table 10-28
(1)
Set-pending
ISPR[0]
shows how the interrupts, or IRQ numbers, map
Clear-pending
ICPR[0]
Active Bit
IABR[0]
11011A–ATARM–04-Oct-10
“NVIC