SAM3N0C Atmel Corporation, SAM3N0C Datasheet - Page 363

• Manufacturer Part Number: SAM3N0C
• Manufacturer: Atmel Corporation

24.15.9
Name:
Address:
Access:
Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC.
Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLR register.
This register can only be written if the WPEN bit is cleared in
• DIV: Divider
• PLLCOUNT: PLL Counter
Specifies the number of Slow Clock cycles x8 before the LOCK bit is set in PMC_SR after CKGR_PLLR is written.
• MUL: PLL Multiplier
0 = The PLL is deactivated.
1 up to 2047 = The PLL Clock frequency is the PLL input frequency multiplied by MUL + 1.
11011A–ATARM–04-Oct-10
DIV
0
1
2 - 255
31
23
15
–
–
7
PMC Clock Generator PLL Register
CKGR_PLLR
0x400E0428
Read-write
30
22
14
–
–
6
29
21
13
1
5
Divider Selected
Divider output is 0
Divider is bypassed (DIV = 1)
Divider output is DIV
28
20
12
–
4
MUL
DIV
“PMC Write Protect Mode Register” on page
27
19
11
–
3
PLLCOUNT
26
18
10
2
MUL
25
17
9
1
374.
SAM3N
24
16
8
0
363