RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 44
RCLXT16706FE
Manufacturer Part Number
RCLXT16706FE
Description
Manufacturer
Intel
Datasheet
1.RCLXT16706FE.pdf
(352 pages)
Specifications of RCLXT16706FE
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
2.97V
Operating Supply Voltage (max)
3.63V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Not Compliant
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Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
44
Table 4.
Pin Description (Sheet 30 of 66)
RXDATA[32]
RXDATA[33]
RXDATA[34]
RXDATA[35]
RXDATA[36]
RXDATA[37]
RXDATA[38]
RXDATA[39]
RXDATA[40]
RXDATA[41]
RXDATA[42]
RXDATA[43]
RXDATA[44]
RXDATA[45]
RXDATA[46]
RXDATA[47]
RXDATA[48]
RXDATA[49]
RXDATA[50]
RXDATA[51]
RXDATA[52]
RXDATA[53]
RXDATA[54]
RXDATA[55]
RXDATA[56]
RXDATA[57]
RXDATA[58]
RXDATA[59]
RXDATA[60]
RXDATA[61]
RXDATA[62]
RXDATA[63]
RXCLK
NOTE: See notes 1, 2, and
Pin Name
E17
Pin
LVTTL
Output
4 mA
LVTTL
Input
Type
3
at the end of the table.
NOTE: The 32 most significant bits of the receive UTOPIA data bus
When the 64-bit operation mode is selected (RcvUWidth = '11', register
R_UICNF), the RXDATA[63:32] bus can be located at one of two
different sets of pins:
Receive UTOPIA Clock. This input clock provides timing for the Intel
IXF6048 receive system interface. RXCLK must cycle at a 104 MHz, or
lower, instantaneous rate.
• If U64Mode (register GOCNF) is set to logic zero, then
• If U64Mode (register GOCNF) is set to logic one, then
RXDATA[63:32] uses the receive TTL line side interface pins. In this
configuration, the device can only use the PECL line side interface.
This configuration may be used in OC-48/OC-48c.
RXDATA[63:32] uses the receive OH/Alarm extraction interface
pins. In this configuration, the device uses only section overhead
extraction. This configuration may be used in OC-12 and Quad OC-
12c modes.
(RXDATA[63:32]) can be located in two different sets of pins.
See
Interface” on page 82
Receive OH/Alarm Extraction Ports” on page
“I/O Pin Equivalence on the Receive TTL Line Side
Description
and
“TTL I/O Pin Equivalence on the
85.
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