RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 338

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
338
RXCLK frequency
RXCLK duty cycle
RXADDR[4:0] and RXENB setup time to RXCLK
RXADDR[4:0] and RXENB hold time from RXCLK
RXCLK rising edge to RXDATA[31:0], RXPRTY, RXSOF, RXEOF,
RXPADL[1:0], RXVAL, RXERR, RXPFA, and RXFA_i (i = 0, 1, 2, 3)
propagation delay
TXCLK frequency
TXCLK duty cycle
TXDATA[31:0], TXADDR[4:0], TXPADL[1:0], TXENB, TXSOF, TXEOF,
TXPRTY, and TXERR setup time to TXCLK
TXDATA[31:0], TXADDR[4:0], TXPADL[1:0], TXENB, TXSOF, TXEOF,
TXPRTY, and TXERR hold time from TXCLK
TXCLK rising edge to TXPFA, TXSFA, and TXFA_i (i = 0, 1, 2, 3)
propagation delay
Table 44. Receive UTOPIA Single Interface Timings for the Configurations Supporting 104
Table 45. Transmit UTOPIA Single Interface Timings for the Configurations Supporting 104
Figure 89. Receive UTOPIA Quad Interface Configured for 104 MHz Operation: 8-Bit Data Bus,
RXVAL_i, RXERR_i, RXFA_i
MHz Operation: 32/16/8-Bit Wide Data Bus, Two Decode-Response Clock Cycles
and No High-Impedance Outputs
MHz Operation: 32/16/8-Bit Wide Data Bus, Two Decode-Response Clock Cycles
and No High-Impedance Outputs
Two Clock Cycle Decode-Response Delay and No High-Impedance Outputs
RXDATA_i[7:0], RXPRTY_i,
RXSOF_i, RXEOF_i,
Parameter
Parameter
RXENB_i
RXCLK_i
VALID OUTPUT
t
ul3Rxsu
VALID INPUT
t
ul3Rxpd
t
ul3Rxh
Symbol
Symbol
t
t
t
t
D
t
ul3Rxsu
ul3Rxpd
D
t
ul3Txpd
f
ul3Txsu
ul3Rxh
f
ul3Txh
ul3Rx
ul3Tx
ul3Rx
ul3Tx
1/f
VALID OUTPUT
ul3Rx
VALID INPUT
Min
Min
2.0
0.5
2.0
0.5
30
30
1
1
Typ
Typ
Max
Max
104
104
70
70
6
6
Datasheet
MHz
Unit
Unit
MHz
ns
ns
ns
%
ns
ns
ns
%