RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 238
RCLXT16706FE
Manufacturer Part Number
RCLXT16706FE
Description
Manufacturer
Intel
Datasheet
1.RCLXT16706FE.pdf
(352 pages)
Specifications of RCLXT16706FE
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
2.97V
Operating Supply Voltage (max)
3.63V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Not Compliant
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Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
11.2.17
238
15:2
Bit
Bit
1
0
8
7
6
5
4
3
2
1
0
Pol_RCI_T0
Pol_TSCI_P3
Pol_TSCI_P2
Pol_TSCI_P1
Pol_TSCI_P0
Pol_RSCI_P3
Pol_RSCI_P2
Pol_RSCI_P1
Pol_RSCI_P0
Unused
Pol_TPCI_P
Pol_RPCI_P
ICPCNF2—Input Clock Polarity Configuration 2 ((000)11H)
This register allows inversion of each individual Intel IXF6048 input clock.
By default, Intel IXF6048 uses the rising edge of each input clock to sample data. When the
polarity configuration bit of an input clock is set to logic one, Intel IXF6048 inverts the clock
before using it, i.e., Intel IXF6048 uses the falling edge of the clock.
Name
Name
'0' = RSCI_0, RPCI_0 and RPCI clock is not inverted.
'1' = RSCI_0, RPCI_0 and RPCI clock is inverted.
'0' = TSCI_P3/N3 is not inverted.
'1' = TSCI_P3/N3 clock is inverted.
'0' = TSCI_P2/N2 clock is not inverted.
'1' = TSCI_P2/N2 clock is inverted.
'0' = TSCI_P1/N1 clock is not inverted.
'1' = TSCI_P1/N1 clock is inverted.
'0' = TSCI_P0/N0 clock is not inverted.
'1' = TSCI_P0/N0 clock is inverted.
'0' = RSCI_P3/N3 is not inverted.
'1' = RSCI_P3/N3 clock is inverted.
'0' = RSCI_P2/N2 clock is not inverted.
'1' = RSCI_P2/N2 clock is inverted.
'0' = RSCI_P1/N1 clock is not inverted.
'1' = RSCI_P1/N1 clock is inverted.
'0' = RSCI_P0/N0 clock is not inverted.
'1' = RSCI_P0/N0 clock is inverted.
'0' = TPCI_P/N clock is not inverted.
'1' = TPCI_P/N clock is inverted.
'0' = RPCI_P/N clock is not inverted.
'1' = RPCI_P/N clock is inverted.
Description
Description
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Datasheet
Default
Default
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
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