RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 175

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

6.4
6.4.1
Datasheet
Figure 48
device. This could be for a single OC-3/12/48 non-concatenated line side input or four OC-1/3/12
concatenated line side inputs. This example corresponds to the following configuration:
Figure 50
device. This could be for a single OC-3/12 non-concatenated line side input or four OC-1/3
concatenated line side inputs. This example corresponds to the following configuration:
Figure 52
mode. This could be for a single OC-3/12 non-concatenated line side input or four OC-1/3
concatenated line side inputs. This example corresponds to the following configuration:
Transmit ATM-UTOPIA Interface
Decode-Response Configuration
XmtDRCnf (channel register T_UICHCNF) sets the decode-response delay for the transmit
interface:
When XmtDRCnf = '0', the decode-response delay in the transmit UTOPIA interface is one clock
cycle:
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RcvUWidth[1:0] = '10' (32-bit interface)
RcvCellStruct = '1' (14-word cell data structure)
RcvDRCnf = '1' (2 clock cycle decode-response time)
RcvMPhyDevCnf = '0' (single PHY device)
RcvUQuad = '0' (single interface)
RcvUWidth[1:0] = '10' (32-bit interface)
RcvCellStruct = '1' (14-word cell data structure)
RcvDRCnf = '1' (2 clock cycle decode-response time)
RcvMPhyDevCnf = '1' (multiple PHY device)
RcvUQuad = '0' (single interface)
RcvUWidth[1:0] = '01' (16-bit interface)
RcvCellStruct = '1' (27-word cell data structure)
RcvDRCnf = '0' (1 clock cycle decode-response time)
RcvMPhyDevCnf = '0' (single PHY device)
RcvUQuad = '0' (single interface)
RcvUWidth[1:0] = '01' (16-bit interface)
RcvCellStruct = '1' (27-word cell data structure)
RcvDRCnf = '0' (1 clock cycle decode-response time)
RcvMPhyDevCnf = '1' (multiple PHY device)
shows an example where the receive interface has been configured as a 32-bit MPHY
shows an example where the receive interface has been configured as a 16-bit single
shows an example where the receive interface has been configured in UTOPIA Level 2
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
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