RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 214

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
10.3
10.3.1
10.3.2
10.3.3
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Interrupt Handling
Interrupt Sources
There are three types of interrupt sources:
Interrupt Enables
In order for an interrupt source to affect the state of the INT output pin, its associated interrupt
enable bit must be set. The setting (whether it is '0' or '1') of the interrupt enables does not affect the
updating of the status registers or counters.
Assuming the interrupt enable for a particular interrupt source is set and the interrupt source is
active, its interrupt bit is set. The primary difference between each interrupt type is the way its
respective interrupt bit is cleared.
Interrupt Clearing
In the discussion below, it is assumed that the example interrupt sources have their interrupt enable
bits set.
Status change interrupt sources have their interrupt bits cleared when their status is read. For
example, say the OofSt bit changes from '0' to '1' (in frame to out of frame). Its interrupt bit is set
by this event. When the microprocessor reads the register containing the OofSt bit, its interrupt bit
is cleared. If the OofSt bit subsequently changes from '1' to '0' (out of frame to in frame) again, its
interrupt bit is set again by this event and then cleared when the status is read.
The interrupt register can be read again only after three internal clock cycles have been completed
since it was last cleared by reading its associated status registers.
It should be noted that updates to status bits are not affected by the interrupt bit state. For example,
the OofSt bit could change from '1' to '0' (generating an interrupt) and then before the
microprocessor reads OofSt, it could change back to '1'. This would have no affect on its interrupt
bit since it would already be set. When the microprocessor reads the OofSt bit, it would read '1'.
Both event interrupts and counter overflow interrupts are cleared when their interrupt registers are
read, as event interrupts and counters do not have any associated status registers.
1. Status change of a monitoring process: For example, the Intel IXF6048 monitors the incoming
2. Event Occurrence: For example, the receive ATM FIFO overflow is considered an event and
3. Counter overflows: For example, the Intel IXF6048 monitors the SONET/SDH frame for BIP
SONET/SDH frames for the correct framing word and updates the LosSt, LofSt, and OofSt
status bits (register (1cc)D8H) indicating the presence or absence of Loss Of Signal, Loss Of
Frame, and Out Of Frame conditions. When the value of these status bits change, an interrupt
(LOS, LOF, and OOF in register (1cc)D0H) is generated, if enabled.
generates interrupts, if enabled.
errors. These errors are recorded in a counter whose overflow causes an interrupt, if enabled.
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