RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 320

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
320
Bit
3:2
6
5
4
1
0
XmtReadEn
XmtFCSErrCnf
XmtFCSErr
XmtFCSCnf[1:0]
XmtACPass
XmtScrEn
Name
XmtReadEn disables the reading of POS-packets from the
transmit FIFO:
'0' = The transmit HDLC controller does not read packets from the
transmit FIFO (even if the FIFO contains data) and maps Flag
characters into the SPE.
'1' = The transmit HDLC controller operates normally, reading
packets from the transmit FIFO (if the FIFO contains data).
XmtReadEn should not be used for transmit Flow Control. Register
T_IPGCTRL offers a better way to do that.
XmtFCSErrCnf configures how XmtFCSErr is used (see below).
'0' = If XmtFCSErr = 1, the next HDLC frame is transmitted with an
error i.e., the FCS field (if used) is inverted prior to transmission.
After inserting the FCS error, XmtFCSErr automatically resets.
'1' = If XmtFCSErr = 1, all the HDLC frames are transmitted with an
FCS error i.e., the FCS field (if used) is inverted prior to
transmission. In this configuration, XmtFCSErr must be set to logic
zero manually.
XmtFCSErr controls the insertion of FCS errors into the
transmitted HDLC frames.
‘0’ = Normal Operation (default) XmtFCSErrCnf is Don’t Care
'1' = See the description in XmtFCSErrCnf.
XmtFCSCnf[1:0] selects the type of Frame Check Sequence (FCS)
inserted in the transmitted frames:
XmtFCSCnf[1:0]
'00'
'01'
'10'
'11'
XmtACPass configures transmission of the HDLC Address and
Control fields:
'0' = The transmit HDLC controller generates the HDLC Address
and Control fields. The Link Layer device writes into the transmit
FIFO only the HDLC information field (PPP frames).
'1' = The transmit HDLC does not generate the HDLC Address and
Control fields. The Link Layer device writes into the transmit FIFO
the HDLC Address, Control and Information field. The transmit
HDLC controller transmits the HDLC Address and Control fields
stored into the FIFO.
XmtScrEn controls the scrambling of the HDLC frames (the
SONET/SDH SPE) by using the self-synchronous scrambler 1 +
X
'0' = The scrambler is disabled.
'1' = The scrambler is enabled.
43
:
# FLAGs
None
Reserved
CRC-16 (CRC-CCITT)
CRC-32
Description
Type
R/W
R/W
R/W
R/W
R/W
R/W
Datasheet
Default
'11'
'1'
'0'
'0'
'1'
'1'