RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 122

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
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Note: In concatenated mode for all line rates, the errors are accumulated in the associated port/interfaces
Note: In non-concatenated mode for STS-3 and STS-12/STM-4 line rates, the errors are accumulated in
Note: In non-concatenated mode for STS-48/STM-16 line rates, the errors are accumulated in port/
4.4.1.4.5 MS-REI Via M1 Byte
This byte is allocated for the Remote Error Indication. Remote BIP errors are accumulated in a 21-
bit counter, accessible via registers MR_BIPCNT. Remote block errors are accumulated in an 17-
bit counter, accessible via registers MR_BLKCNT.
MR_BIPCNT/MR_BLKCNT register (for example, for traffic received on port interface 0, the
values would be accumulated in register 0’s MR_BIPCNT/MR_BLKCNT).
port/interface 2’s MR_BIPCNT/MR_BLKCNT register (for example, for traffic received on port
interface 0, the only line side port usable with non-concatenated traffic, the values would be
accumulated in register 2’s MR_BIPCNT/MR_BLKCNT).
interface 0’s MR_BIPCNT/MR_BLKCNT register (for example, for traffic received on port
interface 0, the only line side port usable with non-concatenated traffic, the values would be
accumulated in register 0’s MR_BIPCNT/MR_BLKCNT).
A block can be considered over a frame or as per STM-1 equivalent (see register configuration
R_MST_C), meaning that an OC-48 contains either 1 or 16 blocks. M1 receive byte is provided
serially at RSOH serial bus output.
4.4.1.4.6 S1 Byte: Synchronization Status
S1[3:0] bits are allocated for Synchronization Status Messages. A change in S1 byte for three
consecutive frames is indicated in register IS_MUX and allows the updating of register R_S1.
Register R_S1 provides microprocessor access to S1 received filtered value. When the value of S1
byte has not been detected identical for 3 consecutive frames, in a window of 16 frames, a
RcvS1Unstable alarm is indicated in register IS_MUX.
S1 receive byte is also provided serially at RSOH serial bus output.
4.4.1.4.7 D4 to D12 Data Communication Channels
This 576-Kbit/s channel (DCC) may be used to by the network management as a data channel. The
data is accessible via pin RMD and the clock is provided by RMDC. D4 to D12 receive bytes are
also provided serially at RSOH serial bus output.
4.4.1.4.8 E2 Byte: Orderwire Byte (Optional)
This 64-Kbit/s channel is used to optionally provide an orderwire channel for voice
communication. The data is accessible via RMOW. The 64-KHz clock and the 8-KHz byte
synchronization signals are used to receive both the E2 and F1 bytes and are provided at pins
ROWC and ROWBYC. Note that the access to this channel is limited in quad processor mode (due
to pin count) as it is multiplexed on the same pin as the DCC channel. E2 receive byte is also
provided serially at RSOH serial bus output.
4.4.1.4.9 National Used and Undefined Bytes of the MSOH
These bytes are only relevant in OC-3/12/48 mode and can only be accessed via the serial RSOH
output.
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