RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 202

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
8.3
8.3.1
8.3.2
8.3.3
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Transmit POS-UTOPIA Interface
Port Selection Mode
The transmit POS-UTOPIA interface can be configured to operate as the ATM-UTOPIA interface
(using a port selection cycle) or as a simple memory mapped device.
Decode-Response Configuration
XmtDRCnf (global register T_UICNF) configures the decode-response delay for the receive
interface:
When XmtDRCnf = '0', the decode-response delay in the receive UTOPIA interface is one clock
cycle:
When XmtDRCnf = '1', the decode-response delay in the receive UTOPIA interface is two clock
cycles:
Single-Device/Multiple-Device Configuration
Intel IXF6048 can be configured to operate as the only device in the interface (driving the outputs
always) or sharing the interface with other PHY devices (driving the outputs only when it is
selected). This feature can be configured independently in the receive and transmit directions.
XmtMPhyDevCnf in global register T_UICNF controls the receive interface:
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RcvDRCnf = '0' (1 clock cycle decode-response time)
RcvMPhyDevCnf = '0' (single PHY device)
When configuration bit XmtSelMode = '0' (global register T_UICNF), the transmit POS-
UTOPIA interface operates in a similar way to the ATM-UTOPIA interface. Two independent
processes run in parallel: the data transfer and the FIFO status polling. TXADDR[4:0] are used
to poll the status of the FIFOs (using the output TXPFA) and to select a port when TXENB
changes from '1' to '0'. Once the port is selected (TXENB = '0'), the transmit address
TXADDR[4:0] can take any value (FIFO status polling using TXPFA).
When configuration bit XmtSelMode = '1' (global register T_UICNF), the transmit POS-
UTOPIA interface is controlled as a memory mapped device. There is no selection cycle or
FIFO status polling, just port addressing. The TXPFA output is not used and the status of each
FIFO is indicated using the direct outputs TXFA_0, TXFA_1, TXFA_2, and TXFA_3.
Nothing happens when TXENB = '1'. If TXENB = '0', the interface writes the word transported
on TXDATA into the FIFO addressed by TXADDR[4:0].
The delay from the transmit address (TXADDR) to the receive polled frame available signal
(TXPFA) is one clock cycle.
The delay from the transmit address (RXADDR) to the receive polled frame available signal
(RXPFA) is two clock cycles.
When XmtMPhyDevCnf = '1', TXPFA is only driven when TXADDR matches the
programmed device address. This setting must be used when Intel IXF6048 shares the
transmit interface with other PHY devices.
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