RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 145

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

4.5.3.2
Datasheet
Receive Section Alarm & APS Serial Bus Timing
RSALFR[i]
RSAL[i]
RSALCK/RMDC[i]
RSALFR[i]
RSAL[i]
Figure 17. Receive Section Alarm and APS Serial Bus Timing
Output data
Output data
Output frame pulse
Output frame pulse
Output clock
(576 KHz)
Transmit Side: TSAL Serial Bus
The transmit side of the serial Alarm and APS interface allows insertion of the remote defect
information (MS-RDI and MS-REI) feedback from the receive, and/or the insertion of the APS
bytes K1 and K2 into the transmit SOH via a serial co- or contra-directional interface. As it can
process four independent sections, Intel IXF6048 provides up to four TSAL interfaces (one per
channel). The co- or contra-directional mode is configured via register T_SC_MSOH.
Contradirectional Interface: This mode simplifies the external processing of the APS protocol as
the timing is supplied by the Intel IXF6048.
Codirectional Interface: This allows a direct connection from the RSAL output port of an Intel
IXF6048 chip to the TSAL input port of a second Intel IXF6048 chip, to provide external feedback
of both RDI and REI defects from receive to transmit.
— The reference clock is supplied by TSALCK[i] at 576-KHz. TSALCK[i] is synchronous
— Frame pulse output TSALFR[i] indicates the expected presence of RDI at TSAL input. It
— The Intel IXF6048 latches the data on the TSAL pin, synchronized with the output timing
— The clock is input on TSALCK[i] at 576-KHz.
— Frame pulse input TSALFR[i] indicates the expected presence of RDI at TSAL input. It is
— The Intel IXF6048 latches the data on the TSAL pin, using the input timing signals. As
Time Slot #1
with the frame rate.
is repeated every 125 µs.
signals.
repeated every 125 µs.
TSALCK[i] might not be synchronous with the transmit frame rate, some information
may be lost once in a while, due to the frequency deviation.
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
Gen RDI
B2 Error(GREI)
SF
Every Frame
Rcv K1 APS filt.
EED
1 frame: 125 µs <=> 72 x RSALCK/RMDC[i] clock cycles
DSD
Rcv. K2 APS Filt.
K1 Unst
K2 Unst.
Time Slot #5
K1 Chge
B1 Error
K2 Chge
GREI[7]
Time Slot #7
8 clock
cycles
GREI[6]
Rcv S1 filtered
GREI[5]
GREI[4]
Unused TS#9
TS #1
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