RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 324

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Intel IXF6048 — 51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
11.14.5
11.14.6
11.14.7
324
31:20
15:7
19:0
15:0
Bit
Bit
Bit
6
5
4
3
Unused
XmtByteCntI
XmtFrmCntI
XmtAbortCntI
XmtFifoUFCntI
Unused
XmtUAFrmCnt[19:0]
XmtFifoUFCnt[15:0]
T_AFCNT—Transmit Aborted Frame Counter ((1cc)47H-(1cc)46H)
T_PFUCNT—Transmit Packet FIFO Underflow Counter ((1cc)48H)
(1cc)47H = Bits[19:16], (1cc)46H = Bits[15:0]
T_POSINT—Transmit POS Interrupt Register ((1cc)49H)
Name
Name
Name
XmtByteCntI sets to logic one when the “transmit byte counter”
(register T_BYTECNT) rolls over.
This interrupt bit clears automatically when this register is read.
XmtFrmCntI sets to logic one when the “transmit frame counter”
(register T_FRMCNT) rolls over.
This interrupt bit clears automatically when this register is read.
XmtAbortCntI sets to logic one when the “transmit aborted frame
counter” (register T_AFCNT) rolls over.
This interrupt bit clears automatically when this register is read.
XmtFifoUFCntI sets to logic one when the “transmit FIFO
underflow counter” (register T_FUFCNT) rolls over.
This interrupt bit clears automatically when this register is read.
XmtAFrmCnt[19:0] counts the number of HDLC frames
aborted by the Link Layer device (by asserting the TXERR
input) during the last accumulation interval. These frames
are mapped in the SONET/SDH SPE and are finished with
an ABORT sequence.
A write to the counter (address (1cc)47H) causes the entire
counter to be loaded into a buffer and then cleared. The
contents of the buffer can then be read.
XmtFifoUFCnt[15:0] counts the number of HDLC frames that
have been aborted by the transmit HDLC controller due to a
FIFO under-run during the last accumulation interval. These
frames are mapped in the SONET/SDH SPE and are
finished with an ABORT sequence.
A write to the counter (address (1cc)48H) causes the entire
counter to be loaded into a buffer and then cleared. The
contents of the buffer can then be read.
Description
Description
Description
Type
Type
Type
R
R
R
R
R
R
Datasheet
Default
Default
Default
00H
00H
'0'
'0'
'0'
'0'