RCLXT16706FE Intel, RCLXT16706FE Datasheet - Page 39

• Manufacturer Part Number: RCLXT16706FE
• Manufacturer: Intel

Specifications of RCLXT16706FE

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Datasheet
Table 4.
Pin Description (Sheet 25 of 66)
TPOH_0
TPOH_1
TPOH_2
TPOH_3
TPOHINS_0
TPOHINS_1
TPOHINS_2
TPOHINS_3
TPOHFR_0
TPOHFR_1
TPOHFR_2
TPOHFR_3
TPOHCK_0
TPOHCK_1
TPOHCK_2
TPOHCK_3
TPAL_0
TPAL_1
TPAL_2
TPAL_3
NOTE: See notes 1, 2, and
Pin Name
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface — Intel IXF6048
Pin
M1
M3
M4
M5
N3
N5
N6
K1
N1
P5
P6
N2
P1
P2
P3
P4
L1
L2
L3
J1
LVTTL
Input
LVTTL
Input
LVTTL
Bidir
4 mA
LVTTL
Bidir
4 mA
LVTTL
Input
Type
3
at the end of the table.
Transmit POH Insertion Bus. TPOH_i (i = 0, 1, 2, 3) inputs the POH
bytes to be inserted in the outgoing SONET/SDH frames on channel #i.
When the transmit path alarm bus is configured in codirectional mode
(TpalBusCnfg = '1', register T_HPT_OPC) TPOH_i and TPOHINS_i (i =
0, 1, 2, 3) are unused inputs.
TPOH_i (i = 0, 1, 2, 3) is clocked in by TPOHCK_i.
Transmit POH Insertion Enable. TPOHINS_i (i = 0, 1, 2, 3) is the
active-high POH insertion enable, controlling the insertion of the bytes
transported on TPOH_i in the SONET/SDH frames generated by
channel #i. The byte transported in TPOH_i (i = 0, 1, 2, 3) is inserted in
the outgoing frame if TPOHINS_i is asserted during its most significant
bit.
TPOHINS_i (i = 0, 1, 2, 3) control pin may be disabled via
microprocessor configuration register T_HPT_C[15] (TPOHINS_Ena =
‘0’ in register address (1cc)E8H).
When the transmit path alarm bus is configured in codirectional mode
(TpalBusCnfg = '1', register T_HPT_OPC), TPOH_i and TPOHINS_i (i =
0, 1, 2, 3) are unused inputs.
TPOHINS_i (i = 0, 1, 2, 3) is clocked in by TPOHCK_i.
Transmit POH Insertion Frame Pulse. TPOHFR_i (i = 0, 1, 2, 3) is an
8-KHz pulse indicating the start of the frames transported on the TPOH_i
and TPAL_i inputs. TpalBusCnfg (register T_HPT_OPC) configures the
transmit path alarm bus as a codirectional or a contradirectional
interface:
TPOHFR_i (i = 0, 1, 2, 3) is clocked out by TPOHCK_i.
Transmit POH Insertion Clock. TPOHCK_i (i = 0, 1, 2, 3) is a 576-KHz
timing reference signal used to clock in the TPOH_i and TPAL_i data on
channel #i. TpalBusCnfg (register T_HPT_OPC) configures the transmit
path alarm bus as a codirectional or a contradirectional interface:
Transmit Path Alarm Bus. TPAL_i (i = 0, 1, 2, 3) allows the insertion of
the remote path defect information (HP-RDI and HP-REI) on channel #i.
The expected position of the “server defect” bit at the TPAL_i input (i = 0,
1, 2, 3) is indicated by the 8-KHz pulse TPOHFR_i. TpalBusCnfg
(register T_HPT_OPC) configures the transmit path alarm bus as a
codirectional or a contradirectional interface.
TPAL_i (i = 0, 1, 2, 3) is clocked in by TPOHCK_i.
• When TpalBusCnfg = '0', TPOHFR_i (i = 0, 1, 2, 3) is configured as
• When TpalBusCnfg = '1', TPOHFR_i (i = 0, 1, 2, 3) is configured as
• When TpalBusCnfg = '0', TPOHCK_i (i = 0, 1, 2, 3) is configured as
• When TpalBusCnfg = '1', TPOHCK_i (i = 0, 1, 2, 3) is configured as
an output pin.
an input pin.
an output pin.
an input pin.
Description
39