KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 82

• Manufacturer Part Number: KIT_TC1797_SK
• Description: KIT STARTER AUDO FUTURE TC1797
• Manufacturer: Infineon Technologies
• Series: Audo Futurer
• Type: MCUr

Specifications of KIT_TC1797_SK

• Contents: Board, Adapters, Cables, CD, Power Supply
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TC1797
• Other names: KITTC1797SKIN

Workaround
Use at least one leading delay in order to avoid this problem.
SSC_AI.026 Master with highest baud rate set generates erroneous phase
error
If the SSC is in master mode, the highest baud rate is initialized and CON.PO =
1 and CON.PH = 0 there will be a phase error on the MRST line already on the
shift edge and not on the latching edge of the shift clock.
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Workaround
Don’t use a phase error in master mode if the baud rate register is programmed
to zero (SSCBR = 0) which means that only the fractional divider is used.
Or program the baud rate register to a value different from zero (SSCBR > 0 )
when the phase error should be used in master mode.
TC1797, EES-AC, ES-AC, AC
Phase error already at shift edge
The master runs with baud rate zero. The internal clock is derived from the
rising and the falling edge. If the baud rate is different from zero there is a
gap between these pulses of these internal generated clocks.
However, if the baud rate is zero there is no gap which causes that the edge
detection is to slow for the "fast" changing input signal. This means that the
input data is already in the first delay stage of the phase detection when the
delayed shift clock reaches the condition for a phase error check. Therefore
the phase error signal appears.
Phase error pulse at the end of transmission
The reason for this is the combination of point 1 and the fact that the end of
the transmission is reached. Thus the bit counter SSCBC reaches zero and
the phase error detection will be switched off.
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Functional Deviations
Rel. 1.3, 18.12.2009
Errata Sheet