KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 39

• Manufacturer Part Number: KIT_TC1797_SK
• Description: KIT STARTER AUDO FUTURE TC1797
• Manufacturer: Infineon Technologies
• Series: Audo Futurer
• Type: MCUr

Specifications of KIT_TC1797_SK

• Contents: Board, Adapters, Cables, CD, Power Supply
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TC1797
• Other names: KITTC1797SKIN

This results in the timing detailed in the table below, where CP1 is the first clock
cycle of the command phase, DHn is the last clock cycle of the Data Hold Phase
and T
Table 7
EXTCLOCK is set to
1) DHn indicates the final Data Hold Phase. If no Data Hold is programmed, this will
2) Data bus will be enabled at the beginning of CP1
Workaround
Adjust the phase lengths for the asynchronous regions to compensate for the
modified signal delays.
FADC_TC.005 Equidistant multiple channel-timers
The description is an example for timer_1 and timer_2, but can also affect all
other combinations of timers.
Timer_1 and Timer_2 are running with different reload-values. Both timers
should start conversions with the requirement of equidistant timing.
Problem description:
Timer_1 becomes zero and starts a conversion. Timer_2 becomes zero during
this conversion is running and sets the conversion-request-bit of channel_2. At
the end of the conversion for channel_1 this request initiates a start for
channel_2. But the Timer_2 is reloaded only when setting the request-bit for
channel_2 and is decremented during the conversion of channel_1.
TC1797, EES-AC, ES-AC, AC
00
01
B
B
be CPn, the final Command Phase.
, 10
CLK
B
, 11
is one period of the EBU clock:
Write Data Signal Timing
B
Delay
Disabled
Driven at:
Start of
CP1
Start of
CP1
39/101
Delay
Enabled
Start of
CP1
End of
CP1
2)
Removed at:
Delay
Disabled
End of
DHn
End of DHn End of DHn
1)
Functional Deviations
Rel. 1.3, 18.12.2009
Delay
Enabled
End of DHn
+ T
+ T
Errata Sheet
CLK
CLK