KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 100

• Manufacturer Part Number: KIT_TC1797_SK
• Description: KIT STARTER AUDO FUTURE TC1797
• Manufacturer: Infineon Technologies
• Series: Audo Futurer
• Type: MCUr

Specifications of KIT_TC1797_SK

• Contents: Board, Adapters, Cables, CD, Power Supply
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TC1797
• Other names: KITTC1797SKIN

SSC_AI.H002 Transmit Buffer Update in Master Mode during Trailing or
Inactive Delay Phase
When the Transmit Buffer register TB is written in master mode after a previous
transmission has been completed, the start of the next transmission (generation
of SCLK pulses) may be delayed in the worst case by up to 6 SCLK cycles (bit
times) under the following conditions:
•
•
No extended leading delay will occur when both TRAIL = 0 and INACT = 0.
This behaviour has no functional impact on data transmission, neither on
master nor slave side, only the data throughput (determined by the master) may
be slightly reduced.
To avoid the extended leading delay, it is recommended to update the Transmit
Buffer after the transmit interrupt has been generated (i.e. after the first SCLK
phase), and before the end of the trailing or inactive delay, respectively.
Alternatively, bit BSY may be polled, and the Transmit Buffer may be written
after a waiting time corresponding to 1 SCLK cycle after BSY has returned to 0
After reset, the Transmit Buffer may be written at any time.
SSC_AI.H003 Transmit Buffer Update in Slave Mode during Transmission
After reset, data written to the Transmit Buffer register TB are directly copied
into the shift register. Further data written to TB are stored in the Transmit Buffer
while the shift register is not yet empty, i.e. transmission has not yet started or
is in progress.
If the Transmit Buffer is written in slave mode during the first phase of the shift
clock SCLK supplied by the master, the contents of the shift register are
overwritten with the data written to TB, and the first bit currently transmitted on
line MRST may be corrupted. No Transmit Error is detected in this case.
TC1797, EES-AC, ES-AC, AC
a trailing delay (SSOTC.TRAIL) > 0 and/or an inactive delay
(SSOTC.INACT) > 0 is configured
the Transmit Buffer is written in the last module clock cycle (f
the inactive delay phase (if INACT > 0), or of the trailing delay phase (if
INACT = 0).
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Application Hints
Rel. 1.3, 18.12.2009
SSC
Errata Sheet
or f
CLC
) of
B
.