KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 29

• Manufacturer Part Number: KIT_TC1797_SK
• Description: KIT STARTER AUDO FUTURE TC1797
• Manufacturer: Infineon Technologies
• Series: Audo Futurer
• Type: MCUr

Specifications of KIT_TC1797_SK

• Contents: Board, Adapters, Cables, CD, Power Supply
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TC1797
• Other names: KITTC1797SKIN

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Workaround
The UPDFL instruction is normally used in one of two situations:
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In the first case, if all the PSW[31:26] bits are cleared by UPDFL, no CAE trap
will be generated.
In the second case, UPDFL may still be used to set the FPU rounding mode,
but in this case the remaining PSW bits, [31:26], must be cleared by UPDFL in
order to avoid generation of an unexpected CAE trap.
In all other cases, where FPU traps are enabled, some other method of
manipulating the PSW user status bits must be used in order to avoid
extraneous CAE trap generation. For instance, if in Supervisor mode the PSW
may be read using the MFCR instruction, the high order PSW bits modified and
written back using the MTCR instruction.
CPU_TC.115 Interrupt may be taken on exit from Halt mode with Inter-
rupts disabled
A problem exists whereby an interrupt may be taken by the TriCore CPU upon
exiting Halt mode, even if interrupts are disabled at that point.
The problem occurs when an interrupt request is received by the TriCore CPU,
with the pending interrupt priority number (PIPN) higher than the current CPU
priority number (CCPN), and interrupts are enabled. In this case, where only the
CPU pipeline status is preventing the interrupt from being taken immediately,
the interrupt is latched and taken as soon as the pipeline can accept an
interrupt. This may cause unexpected behavior whilst debugging, where
TC1797, EES-AC, ES-AC, AC
After execution of the UPDFL instruction, one or more of the PSW[31:26]
bits are set - either the PSW bit(s) are set by UPDFL or were set prior to
execution and not cleared by the UPDFL instruction.
FPU traps are enabled for one of the asserted PSW[31:26] bits, via the
corresponding FPU_TRAP_CON.FxE bit being set.
The FPU_TRAP_CON.TST CSFR bit is clear - no previous FPU trap has
been generated without the subsequent clearing of FPU_TRAP_CON.TST.
Clearing the FPU sticky flags held in PSW[30:26].
Setting the FPU rounding mode bits in PSW[25:24].
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Functional Deviations
Rel. 1.3, 18.12.2009
Errata Sheet