KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 37

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KIT_TC1797_SK

Manufacturer Part Number
KIT_TC1797_SK
Description
KIT STARTER AUDO FUTURE TC1797
Manufacturer
Infineon Technologies
Series
Audo Futurer
Type
MCUr

Specifications of KIT_TC1797_SK

Contents
Board, Adapters, Cables, CD, Power Supply
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
TC1797
Other names
KITTC1797SKIN
Errata Sheet
Functional Deviations
movh.a a0, #0x8000 ;; Cachei operand is random non-
protected cacheable address.
cachei.wi [a0]
;; The DLB gets invalidated regardless
of the value in a0.
If the user is not concerned in invalidating the DMI line buffer but simply
guaranteeing its coherency with external memory then there is another simple
workaround. This consists in issueing a read to a dummy cacheable address
pointing outside the 16-byte block containing the next required data. Access to
the next required data will then necessarily result in a refill and the resulting data
will be coherent. This is what the following code does (a0 contains a dummy
address and a1 contains the address for the user's required data).
movh.a a0, #0x8000 ;; Dummy address is 0x80000000.
ld.w d0, [a0]
;; a0 has to point to different 16-byte
block than a1.
ld.w d0, [a1]
;; This load will be executed fresh from
memory with a refill.
;; Read data will be coherent with rest
of memory.
EBU_TC.020 BAA Delay Options Controlled by Wrong Register Field
The timing options for the BAA signal are specified as being controlled by the
settings of the BUSRCONx.EXTCLOCK and BUSRCONx.EBSE register fields.
In the implementation of the EBU, the logic controlling BAA timing was
connected to the BUSRCONx.ECSE field instead of BUSRCONx.EBSE.
Workaround
Use the BUSRCONx.ECSE field to control the desired timing option for the BAA
signal.
TC1797, EES-AC, ES-AC, AC
37/101
Rel. 1.3, 18.12.2009

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