KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 18

• Manufacturer Part Number: KIT_TC1797_SK
• Description: KIT STARTER AUDO FUTURE TC1797
• Manufacturer: Infineon Technologies
• Series: Audo Futurer
• Type: MCUr

Specifications of KIT_TC1797_SK

• Contents: Board, Adapters, Cables, CD, Power Supply
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TC1797
• Other names: KITTC1797SKIN

Note: In the current TriCore1 CPU implementation, load accesses are initiated
Example
In this example, the half-word store is to address 0xD0000834 and is
immediately followed by a load instruction, so is directed to the store buffer. The
TC1797, EES-AC, ES-AC, AC
...
LDA
LDA
LDA
...
st.h [a12]0x14, d7
ld.w d6, [a8]
add
ld.d [a12/a13+c], d0/d1 ; Circular Buffer wrap, 32+32
...
from the DEC pipeline stage whilst store accesses are initiated from the
following EXE pipeline stage. To avoid memory port contention problems
when a load follows a store instruction, the CPU contains a single store
buffer. In the case where a store instruction (in EXE) is immediately
followed by a load instruction (in DEC), the store is directed to the CPU
store buffer and the load operation overtakes the store. The store is then
committed to memory from the store buffer on the next store instruction or
non-memory access cycle. The store buffer is only used for store
accesses to ‘local’ memories - LDRAM or DCache. Store instructions to
bus-based memories are always executed immediately (in-order). A store
buffer conflict is detected when a load instruction is encountered which
targets an address for which at least part of the requested data is currently
held in the CPU store buffer. In this store buffer conflict scenario, the load
instruction is cancelled, the store committed to memory from the store
buffer and then the load re-started. In systems with an enabled MMU and
where either the store buffer or load instruction targets an address
undergoing PTE-based translation, the conflict detection is just performed
on address bits (9:0), since higher order bits may be modified by
translation and a conflict cannot be ruled out. In other systems (no MMU,
MMU disabled), conflict detection is performed on the complete address.
a8,
a12, 0xD0000820 ; Circular Buffer Base
a13, 0x00180014 ; Circular Buffer Limit and Index
d4, d3, d2
0xD000000E ; Address of un-aligned load
; Store causing conflict
; Un-aligned load, split 16+16
; Optional IP instruction
; conflict with st.h
18/101
Functional Deviations
Rel. 1.3, 18.12.2009
Errata Sheet