KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 28
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KIT_TC1797_SK
Manufacturer Part Number
KIT_TC1797_SK
Description
KIT STARTER AUDO FUTURE TC1797
Manufacturer
Infineon Technologies
Series
Audo Futurer
Type
MCUr
Datasheets
1.SAK-TC1797-512F180E_AC.pdf
(190 pages)
2.KIT_TC1791_SK.pdf
(46 pages)
3.KIT_TC1797_SK.pdf
(101 pages)
4.KIT_TC1797_SK.pdf
(12 pages)
Specifications of KIT_TC1797_SK
Contents
Board, Adapters, Cables, CD, Power Supply
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
TC1797
Other names
KITTC1797SKIN
- SAK-TC1797-512F180E_AC PDF datasheet
- KIT_TC1791_SK PDF datasheet #2
- KIT_TC1797_SK PDF datasheet #3
- KIT_TC1797_SK PDF datasheet #4
- Current page: 28 of 101
- Download datasheet (4Mb)
interruptReal:
Again it is preferred that this method be used immediately at the beginning of
the interrupt handler, since this approach works straightforwardly provided
there is no state in the Upper Context registers or on the interrupt stack that is
required by the interrupt handler when it returned to. Although it is possible to
adapt this approach to operate later during interrupt handling, additional steps
need to be taken to ensure the correct state is maintained when returning to the
interrupt handler.
CPU_TC.114 CAE Trap may be generated by UPDFL instruction
UPDFL is a User mode instruction implemented as part of the TriCore1
Floating-Point Unit (FPU), which allows individual bits of the PSW user status
bits, PSW[31:24], to be set or cleared. Contrary to early revisions of the
TriCore1.3.1 architecture manual, and in contrast to most other FPU
instructions, the UPDFL instruction should not generate Co-Processor
Asynchronous Error (CAE) traps. However, in certain circumstances the
TriCore1.3.1 FPU will generate CAE traps for UPDFL instructions.
The TriCore1.3.1 FPU will generate a CAE trap upon execution of the UPDFL
instruction in the following situation:
TC1797, EES-AC, ES-AC, AC
; force CSA into memory
dsync
sh.h
insert d15, d14, d15, #6, #16
mov.a
; load trap value of d15 from CSA
ld.w
mov.a
movh.a a11, #@his(interuptReal)
lea
; jump to trap handler, will return to interruptReal
ji
; the remaining part of the interrupt handler
...
d14, d15, #12
a15, d15
d15, [a15]0x3C
a15, a11
a11, [a11]@los(interruptReal)
a15
28/101
Functional Deviations
Rel. 1.3, 18.12.2009
Errata Sheet
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