KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 20

• Manufacturer Part Number: KIT_TC1797_SK
• Description: KIT STARTER AUDO FUTURE TC1797
• Manufacturer: Infineon Technologies
• Series: Audo Futurer
• Type: MCUr

Specifications of KIT_TC1797_SK

• Contents: Board, Adapters, Cables, CD, Power Supply
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TC1797
• Other names: KITTC1797SKIN

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Additionally, one of the following further conditions must also be present for the
problem to occur:
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In these very specific circumstances the conflict between the load instruction
and store buffer contents is not detected and the load instruction overtakes the
store, returning the data value prior to the store operation.
Note: In the current TriCore1 CPU implementation, load accesses are initiated
TC1797, EES-AC, ES-AC, AC
The CPU store buffer contains a byte store instruction, st.b, targeting the
base address + 0x1 of a circular buffer.
A word load instruction, ld.w, is executed using circular addressing mode,
targetting the same circular buffer as the buffered byte store.
This word load is only half-word aligned and encounters the circular buffer
wrap-around condition such that the second, wrapped, access of the load
instruction to the bottom of the circular buffer targets the same address as
the byte store held in the store buffer.
The circular buffer base address for the word load is double-word but not
quad-word (128-bit) aligned - i.e. the base address has bits (3:0) = 0x8 with
the conflicting byte store having address bits (3:0) = 0x9, OR,
The circular buffer base address for the word load is quad-word (128-bit)
aligned and the circular buffer size is an odd number of words - i.e. the base
address has bits (3:0) = 0x0 with the conflicting byte store having address
bits (3:0) = 0x1.
from the DEC pipeline stage whilst store accesses are initiated from the
following EXE pipeline stage. To avoid memory port contention problems
when a load follows a store instruction, the CPU contains a single store
buffer. In the case where a store instruction (in EXE) is immediately
followed by a load instruction (in DEC), the store is directed to the CPU
store buffer and the load operation overtakes the store. The store is then
committed to memory from the store buffer on the next store instruction or
non-memory access cycle. The store buffer is only used for store
accesses to ‘local’ memories - LDRAM or DCache. Store instructions to
bus-based memories are always executed immediately (in-order). A store
buffer conflict is detected when a load instruction is encountered which
targets an address for which at least part of the requested data is currently
held in the CPU store buffer. In this store buffer conflict scenario, the load
instruction is cancelled, the store committed to memory from the store
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Functional Deviations
Rel. 1.3, 18.12.2009
Errata Sheet