KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 19

• Manufacturer Part Number: KIT_TC1797_SK
• Description: KIT STARTER AUDO FUTURE TC1797
• Manufacturer: Infineon Technologies
• Series: Audo Futurer
• Type: MCUr

Specifications of KIT_TC1797_SK

• Contents: Board, Adapters, Cables, CD, Power Supply
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TC1797
• Other names: KITTC1797SKIN

word load from address 0xD000000E is split into 2 half-word accesses, since it
spans a 128-bit boundary in LDRAM. The double-word load encounters the
circular buffer wrap condition and should be split into 2 word accesses, to the
top and bottom of the circular buffer. In addition, the first circular buffer access
conflicts with the store to address 0xD0000834. Due to the bug, after the store
buffer is flushed, the first access takes the transfer data size from the second
part of the un-aligned load and only 16-bits of data are read. Note that the
presence of an optional IP instruction between the two load transactions does
not prevent the problem, since the load transactions are back-to-back in the LS
pipeline.
Workaround
Where it cannot be guaranteed that a word or double-word load or store
instruction using circular addressing mode will not encounter one of the corner
cases detailed above which may lead to incorrect behaviour, one NOP
instruction should be inserted prior to the load or store instruction using circular
addressing mode.
CPU_TC.109 Circular Addressing Load can overtake conflicting Store in
Store Buffer
In a specific set of circumstances, a load instruction using circular addressing
mode may overtake a conflicting store held in the TriCore1 CPU store buffer.
The problem occurs in the following situation:
TC1797, EES-AC, ES-AC, AC
...
LDA
LDA
LDA
...
ld.w d6, [a8]
add
nop
st.d [a12/a13+c], d0/d1 ; Circular Buffer wrap, 32+32
...
a8,
a12, 0xD0000820 ; Circular Buffer Base
a13, 0x00180014 ; Circular Buffer Limit and Index
d4, d3, d2
0xD000000E ; Address of un-aligned load
; Un-aligned load, split 16+16
; Optional IP instruction
; Bug workaround
19/101
Functional Deviations
Rel. 1.3, 18.12.2009
Errata Sheet