KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 23

• Manufacturer Part Number: KIT_TC1797_SK
• Description: KIT STARTER AUDO FUTURE TC1797
• Manufacturer: Infineon Technologies
• Series: Audo Futurer
• Type: MCUr

Specifications of KIT_TC1797_SK

• Contents: Board, Adapters, Cables, CD, Power Supply
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: TC1797
• Other names: KITTC1797SKIN

recoverable system errors, with some system state already lost, maintaining
correct behaviour is not critical. However, due to the bug, it is no longer straight-
forward to discriminate FCU traps from other context management (Class 3)
traps. Since the read and write pointers to the register banks are incorrect in the
bug situation, the update of D15 with the Trap Identification Number (TIN) will
write to one bank whilst the read of D15 in the trap handler will read the other
(incorrect) bank, returning an invalid TIN. For similar reasons, the upper context
GPRs are unusable in an FCU trap handler, since register read and write
operations may target different banks.
The problem occurs in the following situation:
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•
•
Workaround
The LCX (Free Context List Limit) pointer should be initialised in order to trap
impending context list overflow before the FCU condition is encountered.
However, in order to maintain some system function in the case of an FCU trap,
the following workaround is required, split into two parts.
Firstly, the Context Management (Class 3) trap handler must be modified to
discriminate FCU traps that incorrectly appear to have a TIN pertaining to
another Class 3 trap due to the bug. This is done by checking for the correct
behaviour of the upper context registers and jumping to the FCU trap handler if
the register file behaviour is found to be in error:
_class3_handler:
TC1797, EES-AC, ES-AC, AC
mov
nop
nop
jne
mov
nop
FCX (Free Context Pointer) points to an invalid location (Null - End of CSA
list, Invalid Segment - Virtual or Peripheral segment).
CALL / CALLA / CALLI instruction is in the decode pipeline stage and would
generate an FCU trap due to the invalid FCX pointer.
Instruction in the Load-Store pipeline execute stage encounters a
synchronous trap condition (VAF-D, VAP-D, MPR, MPW, MPP, MPN, ALN,
MEM, DSE, SOVF, OVF), which would also be converted into an FCU trap.
d12, #7
d12, #7, _fcu_handler
d12, #-8
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Functional Deviations
Rel. 1.3, 18.12.2009
Errata Sheet