KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 21

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KIT_TC1797_SK

Manufacturer Part Number
KIT_TC1797_SK
Description
KIT STARTER AUDO FUTURE TC1797
Manufacturer
Infineon Technologies
Series
Audo Futurer
Type
MCUr

Specifications of KIT_TC1797_SK

Contents
Board, Adapters, Cables, CD, Power Supply
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
TC1797
Other names
KITTC1797SKIN
Example - Case 1
In this example the circular buffer base address is double-word but not quad-
word aligned. The byte store to address 0xD0001009 is immediately followed
by a load operation and is placed in the CPU store buffer. The word load
instruction encounters the circular buffer wrap condition and is split into 2 half-
word accesses, to the top (0xD0001016) and bottom (0xD0001008) of the
circular buffer. The first load access completes correctly, but, due to the bug,
the second access overtakes the store operation and returns the previous half-
word from 0xD0001008.
Example - Case 2
In this example the circular buffer base address is quad-word aligned but the
buffer size is an odd number of words (0x14 = 5 words). The byte store to
address 0xD0001001 is immediately followed by a load operation and is placed
TC1797, EES-AC, ES-AC, AC
...
LDA
LDA
...
st.b [a12]0x1, d2
ld.w d6, [a12/a13+c] ; Circular Buffer wrap, 16+16
...
...
LDA
LDA
...
st.b [a12]0x1, d2
ld.w d6, [a12/a13+c] ; Circular Buffer wrap, 16+16
...
buffer and then the load re-started. In systems with an enabled MMU and
where either the store buffer or load instruction targets an address
undergoing PTE-based translation, the conflict detection is just performed
on address bits (9:0), since higher order bits may be modified by
translation and a conflict cannot be ruled out. In other systems (no MMU,
MMU disabled), conflict detection is performed on the complete address.
a12, 0xD0001008 ; Circular Buffer Base
a13, 0x00180016 ; Circular Buffer Limit and Index
a12, 0xD0001000 ; Circular Buffer Base
a13, 0x00140012 ; Circular Buffer Limit and Index
; Store to byte offset 0x9
; Store to byte offset 0x1
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Functional Deviations
Rel. 1.3, 18.12.2009
Errata Sheet

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