LSM320DLTR STMicroelectronics, LSM320DLTR Datasheet - Page 48

• Manufacturer Part Number: LSM320DLTR
• Description: IC LINEAR
• Manufacturer: STMicroelectronics

Specifications of LSM320DLTR

• Lead Free Status / Rohs Status: Compliant

Registers description
7.41
7.42
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Table 98.
INT1_THS_ZL_G (37h)
Table 99.
Table 100. INT1_THS_ZL_G description
INT1_DURATION_G (38h)
Table 101. INT1_DURATION_G register
Table 102. INT1_DURATION_G description
D6 - D0 bits set the minimum duration of the interrupt event to be recognized. Duration steps
and maximum values depend on the ODR chosen.
WAIT bit has the following meaning:
Wait =’0’: the interrupt falls immediately if signal crosses the selected threshold
Wait =’1’: if signal crosses the selected threshold, the interrupt falls only after the duration
has counted a number of samples at the selected data rate, written into the duration counter
register.
WAIT
D6 - D0
THSZ14 - THSZ9
THSZ7
THSZ7 - THSZ0
WAIT
INT1_THS_ZH_G description
INT1_THS_ZL_G register
THSZ6
D6
WAIT enable. Default value: 0 (0: disable; 1: enable)
Duration value. Default value: 000 0000
Interrupt threshold. Default value: 0000 0000
Interrupt threshold. Default value: 0000 0000
THSZ5
D5
Doc ID 018845 Rev 1
THSZ4
D4
THSZ3
D3
THSZ2
D2
THSZ1
D1
LSM320DL
THSZ0
D0