LSM320DLTR STMicroelectronics, LSM320DLTR Datasheet - Page 46

• Manufacturer Part Number: LSM320DLTR
• Description: IC LINEAR
• Manufacturer: STMicroelectronics

Specifications of LSM320DLTR

• Lead Free Status / Rohs Status: Compliant

Registers description
7.36
7.37
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Table 88.
INT1_CFG_G (30h)
Table 89.
1. This bit must be set to ‘0’ for correct operation.
Table 90.
Configuration register for interrupt source.
INT1_SRC_G (31h)
Table 91.
WTM
OVRN
EMPTY
FSS4-FSS1
AND/OR
LIR
ZHIE
ZLIE
XHIE
XLIE
AND/OR
0
FIFO_SRC_G register description
INT1_CFG_G register
INT1_CFG_G description
INT1_SRC_G register
AND/OR combination of interrupt events. Default value: 0
(0: OR combination of interrupt events 1: AND combination of interrupt events
Latch interrupt request. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
Cleared by reading INT1_SRC reg.
Enable interrupt generation on Z high event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured accel. value
higher than preset threshold)
Enable interrupt generation on Z low event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured accel. value
lower than preset threshold)
Enable interrupt generation on X high event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured accel. value
higher than preset threshold)
Enable interrupt generation on X low event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured accel. value
lower than preset threshold)
LIR
IA
Watermark status. (0: FIFO filling is lower than WTM level; 1: FIFO filling is equal
or higher than WTM level)
Overrun bit status.
(0: FIFO is not completely filled; 1:FIFO is completely filled)
FIFO empty bit.
(0: FIFO not empty; 1: FIFO empty)
FIFO stored data level
ZHIE
ZH
Doc ID 018845 Rev 1
ZLIE
ZL
0
--
(1)
0
--
(1)
XHIE
XH
LSM320DL
XLIE
XL