LSM320DLTR STMicroelectronics, LSM320DLTR Datasheet - Page 30

• Manufacturer Part Number: LSM320DLTR
• Description: IC LINEAR
• Manufacturer: STMicroelectronics

Specifications of LSM320DLTR

• Lead Free Status / Rohs Status: Compliant

Registers description
7
7.1
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Registers description
The device contains a set of registers which are used to control its behavior and to retrieve
acceleration, angular rate and temperature data. The registers address, made of 7 bits, is
used to identify them and to write the data through serial interface.
CTRL_REG1_A (20h)
Table 19.
Table 20.
ODR<3:0> is used to set power mode and ODR selection. In
resulting in a combination of ODR<3:0> are reported.
Table 21.
0
0
0
0
0
0
0
0
1
1
ODR3
ODR3
ODR3-0
LPen
Zen
Xen
Yen
0
0
0
0
1
1
1
1
0
0
CTRL_REG1_A register
CTRL_REG1_A description
Data rate configuration
ODR2
ODR2
Data rate selection. Default value: 0
(0000: power-down; Others: refer to
Low power mode enable. Default value: 0
(0: normal mode; 1: low power mode)
Z axis enable. Default value: 1
(0: Z axis disabled; 1: Z axis enabled)
Y axis enable. Default value: 1
(0: Y axis disabled; 1: Y axis enabled)
X axis enable. Default value: 1
(0: X axis disabled; 1: X axis enabled)
0
0
1
1
0
0
1
1
0
0
ODR1
ODR1
Doc ID 018845 Rev 1
0
1
0
1
0
1
0
1
0
1
ODR0
ODR0
Power down mode
Normal / low power mode (1 Hz)
Normal / low power mode (10 Hz)
Normal / low power mode (25 Hz)
Normal / low power mode (50 Hz)
Normal / low power mode (100 Hz)
Normal / low power mode (200 Hz)
Normal / low power mode (400 Hz)
Low power mode (1.620 kHz)
Normal (1.344 kHz) / Low Power mode (5.376 kHz)
Table
LPen
21., “Data rate configuration”)
Power mode selection
Zen
Table 21
all the frequencies
Yen
LSM320DL
Xen