LSM320DLTR STMicroelectronics, LSM320DLTR Datasheet - Page 39

• Manufacturer Part Number: LSM320DLTR
• Description: IC LINEAR
• Manufacturer: STMicroelectronics

Specifications of LSM320DLTR

• Lead Free Status / Rohs Status: Compliant

LSM320DL
7.23
7.24
Table 59.
TIME WINDOW_A (3Dh)
Table 60.
Table 61.
CTRL_REG1_G (20h)
Table 62.
1. This bit must be set to ‘0’ for correct operation.
Table 63.
DR<1:0> is used to set ODR selection. BW <1:0> is used to set Bandwidth selection.
Table 64
TLA7-TLA0
TW7
TW7-TW0
DR1-DR0
BW1-BW0
PD
Zen
Xen
DR1
shows all frequencies resulting in combination of DR / BW bits.
TW6
TIME_LATENCY_A description
TIME_WINDOW_A register
TIME_WINDOW_A description
CTRL_REG1_G register
CTRL_REG1_G description
Output data rate selection. Refer to
Bandwidth selection. Refer to
Power-down mode enable. Default value: 0
(0: power-down mode, 1: normal mode or sleep mode)
Z axis enable. Default value: 1
(0: Z axis disabled; 1: Z axis enabled)
X axis enable. Default value: 1
(0: X axis disabled; 1: X axis enabled)
DR0
CLICK-CLICK time latency. Default value: 000 0000
CLICK-CLICK time window
TW5
BW1
Doc ID 018845 Rev 1
TW4
BW0
Table 64
Table 64
TW3
PD
TW2
Zen
Registers description
TW1
0
(1)
TW0
Xen
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