LSM320DLTR STMicroelectronics, LSM320DLTR Datasheet - Page 42

• Manufacturer Part Number: LSM320DLTR
• Description: IC LINEAR
• Manufacturer: STMicroelectronics

Specifications of LSM320DLTR

• Lead Free Status / Rohs Status: Compliant

Registers description
7.27
7.28
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Table 71.
CTRL_REG4_G (23h)
Table 72.
1. This bit must be set to ‘0’ for correct operation.
Table 73.
CTRL_REG5_G (24h)
Table 74.
Table 75.
PP_OD
I2_DRDY
I2_WTM
I2_ORun
I2_Empty
BDU
BLE
FS1-FS0
SIM
BOOT
FIFO_EN
HPen
BOOT
BDU
FIFO_EN
CTRL_REG3_G description (continued)
CTRL_REG4_G register
CTRL_REG4_G description
CTRL_REG5_G register
CTRL_REG5_G description
BLE
Push-pull/open drain. Default value: 0. (0: push-pull; 1: open drain)
Date ready on DRDY/INT2. Default value 0. (0: disable; 1: enable)
FIFO watermark interrupt on DRDY/INT2. Default value: 0. (0: disable; 1: enable)
FIFO overrun interrupt on DRDY/INT2. Default value: 0. (0: disable; 1: enable)
FIFO empty interrupt on DRDY/INT2. Default value: 0. (0: disable; 1: enable)
Reboot memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
FIFO enable. Default value: 0
(0: FIFO disable; 1: FIFO enable)
High pass filter enable. Default value: 0
(0: HPF disabled; 1: HPF enabled, see
Block data update. Default value: 0
(0: continuous update; 1: output registers not updated until MSB and LSB
reading)
Big/little endian data selection. Default value 0.
(0: data LSB @ lower address; 1: data MSB @ lower address)
Full scale selection. Default value: 00
(00: 250 dps; 01: 500 dps; 10: 2000 dps; 11: 2000 dps)
SPI serial interface mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface).
FS1
--
Doc ID 018845 Rev 1
HPen
FS0
INT1_Sel1 INT1_Sel0
--
Figure
12)
0
(1)
Out_Sel1
0
(1)
LSM320DL
Out_Sel0
SIM